| /netbsd-6-1-5-RELEASE/sys/external/bsd/drm/dist/shared-core/ |
| H A D | i915_irq.c | 39 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
192 iir = I915_READ(IIR);
199 * Clear the PIPE(A|B)STAT regs before the IIR
215 I915_WRITE(IIR, iir);
502 I915_WRITE(IIR, I915_READ(IIR));
535 I915_WRITE(IIR, I915_READ(IIR));
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| H A D | i915_suspend.c | 337 dev_priv->saveIIR = I915_READ(IIR);
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| H A D | i915_reg.h | 210 #define IIR 0x020a4 macro
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| /netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/opcodes/ |
| H A D | i370-opc.c | 441 #define IIR I370_OPCODE_ESA390_IR
451 #define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390
621 { "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} },
706 { "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} },
790 { "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
791 { "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
794 { "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
795 { "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
796 { "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
797 { "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R
436 #define IIR macro
[all...] |
| /netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/opcodes/ |
| H A D | i370-opc.c | 441 #define IIR I370_OPCODE_ESA390_IR
451 #define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390
621 { "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} },
706 { "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} },
790 { "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
791 { "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
794 { "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
795 { "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
796 { "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
797 { "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R
436 #define IIR macro
[all...] |
| /netbsd-6-1-5-RELEASE/sys/arch/mmeye/mmeye/ |
| H A D | machdep.c | 585 #define IIR 2 macro
613 tmp = INP(IIR);
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| /netbsd-6-1-5-RELEASE/sys/arch/sandpoint/sandpoint/ |
| H A D | satmgr.c | 167 #define IIR 2 macro
617 iir = CSR_READ(sc, IIR) & IIR_IMASK;
635 iir = CSR_READ(sc, IIR) & IIR_IMASK;
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