Searched refs:ICU_INT_HWMASK (Results 1 - 8 of 8) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/arch/arm/xscale/
H A Di80321_intr.h60 : "r" (intr_enabled & ICU_INT_HWMASK));
78 hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~i80321_imask[new];
H A Di80321_icu.c140 : "r" (intr_steer & ICU_INT_HWMASK));
485 hwpend |= ((i80321_ipending & ICU_INT_HWMASK) & ~imask);
H A Di80321reg.h363 #define ICU_INT_HWMASK (0xffffffff & \ macro
H A Dpxa2x0reg.h143 #define ICU_INT_HWMASK 0xffffff00 macro
/netbsd-6-1-5-RELEASE/sys/arch/arm/footbridge/
H A Dfootbridge_intr.h74 #define ICU_INT_HWMASK (0xffffffff & ~(INT_SWMASK | (1U << IRQ_RESERVED3))) macro
85 uint32_t tmp = intr_enabled & ICU_INT_HWMASK;
104 hwpend = footbridge_ipending & ICU_INT_HWMASK & ~footbridge_imask[ipl];
H A Dfootbridge_irqhandler.c332 hwpend |= (footbridge_ipending & ICU_INT_HWMASK) & ~imask;
/netbsd-6-1-5-RELEASE/sys/arch/arm/s3c2xx0/
H A Ds3c2800_intr.c93 while ((irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK) != 0) {
H A Ds3c2800reg.h100 #define ICU_INT_HWMASK 0x1fffffff macro

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