| /netbsd-6-1-5-RELEASE/sys/arch/x86/include/ |
| H A D | ieeefp.h | 15 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/sys/arch/alpha/include/ |
| H A D | ieeefp.h | 49 #define FP_AA_FLAGS (FP_X_INV | FP_X_DZ | FP_X_OFL | FP_X_UFL | FP_X_IMP)
56 #define float_set_invalid() float_raise(FP_X_INV)
61 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/sys/arch/powerpc/include/ |
| H A D | ieeefp.h | 38 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/sys/arch/sh3/include/ |
| H A D | ieeefp.h | 35 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/sys/arch/sparc/include/ |
| H A D | ieeefp.h | 35 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/sys/arch/hppa/include/ |
| H A D | ieeefp.h | 34 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/sys/arch/m68k/include/ |
| H A D | ieeefp.h | 40 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/sys/arch/mips/include/ |
| H A D | ieeefp.h | 38 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/sys/arch/arm/include/ |
| H A D | ieeefp.h | 39 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
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| /netbsd-6-1-5-RELEASE/lib/libc/arch/powerpc64/gen/ |
| H A D | fpsetsticky.c | 62 * FPSCR_VX (aka FP_X_INV) is not a sticky bit but a summary of the
63 * all the FPSCR_VX* sticky bits. So when FP_X_INV is cleared then
66 if ((mask & FP_X_INV) == 0)
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| /netbsd-6-1-5-RELEASE/lib/libc/arch/powerpc/gen/ |
| H A D | fpsetsticky.c | 65 * FPSCR_VX (aka FP_X_INV) is not a sticky bit but a summary of the
66 * all the FPSCR_VX* sticky bits. So when FP_X_INV is cleared then
69 if ((mask & FP_X_INV) == 0)
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| /netbsd-6-1-5-RELEASE/tests/lib/libc/gen/ |
| H A D | t_fpsetmask.c | 179 { f_inv, FP_X_INV, FPE_FLTINV },
187 { d_inv, FP_X_INV, FPE_FLTINV },
195 { ld_inv, FP_X_INV, FPE_FLTINV },
322 fp_except_t msk, lst[] = { FP_X_INV, FP_X_DZ, FP_X_OFL, FP_X_UFL };
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| H A D | t_siginfo.c | 316 fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
367 fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
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| /netbsd-6-1-5-RELEASE/sys/arch/alpha/alpha/ |
| H A D | fp_complete.c | 371 fpcr |= (disables & (FP_X_OFL | FP_X_DZ | FP_X_INV)) << (49 - 0);
373 # if !(FP_X_INV == 1 && FP_X_DZ == 2 && FP_X_OFL == 4 && \
526 float_raise(FP_X_INV);
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| /netbsd-6-1-5-RELEASE/lib/libc/arch/arm/softfloat/ |
| H A D | softfloat.h | 104 float_flag_invalid = FP_X_INV
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| /netbsd-6-1-5-RELEASE/lib/libc/arch/m68k/softfloat/ |
| H A D | softfloat.h | 104 float_flag_invalid = FP_X_INV
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| /netbsd-6-1-5-RELEASE/lib/libc/arch/mips/softfloat/ |
| H A D | softfloat.h | 106 float_flag_invalid = FP_X_INV
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| /netbsd-6-1-5-RELEASE/lib/libc/arch/powerpc/softfloat/ |
| H A D | softfloat.h | 104 float_flag_invalid = FP_X_INV
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| /netbsd-6-1-5-RELEASE/lib/libc/arch/sh3/softfloat/ |
| H A D | softfloat.h | 104 float_flag_invalid = FP_X_INV
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| /netbsd-6-1-5-RELEASE/lib/libc/arch/sparc64/softfloat/ |
| H A D | softfloat.h | 106 float_flag_invalid = FP_X_INV
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| /netbsd-6-1-5-RELEASE/regress/lib/libc/ieeefp/testfloat/include/ |
| H A D | softfloat.h | 139 float_flag_invalid = FP_X_INV
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| /netbsd-6-1-5-RELEASE/sys/lib/libkern/ |
| H A D | softfloat.h | 155 float_flag_invalid = FP_X_INV
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| /netbsd-6-1-5-RELEASE/regress/lib/libc/ieeefp/testfloat/ |
| H A D | systfloat.c | 96 & (FP_X_IMP | FP_X_UFL | FP_X_OFL | FP_X_DZ | FP_X_INV);
|