Searched refs:DCR_MAL0_TXEOBISR (Results 1 - 2 of 2) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/arch/powerpc/ibm4xx/dev/
H A Dmal.c144 while ((tcei = mfdcr(DCR_MAL0_TXEOBISR))) {
147 mtdcr(DCR_MAL0_TXEOBISR, MAL0__XCAR_CHAN(chan));
/netbsd-6-1-5-RELEASE/sys/arch/powerpc/include/ibm4xx/
H A Ddcr4xx.h203 #define DCR_MAL0_TXEOBISR 0x186 /* Tx End of Buffer Interrupt Status Register */ macro

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