Searched refs:CHIP_W1_SYS_START (Results 1 - 25 of 32) sorted by relevance

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/netbsd-6-1-5-RELEASE/sys/arch/mips/rmi/
H A Drmixl_iobus_space.c66 #define CHIP_W1_SYS_START(v) (((struct rmixl_config *)(v))->rc_flash_pbase) macro
67 #define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_FLASH_BAR_MASK_MAX)
H A Drmixl_obio_eb_space.c59 #define CHIP_W1_SYS_START(v) (((struct rmixl_config *)(v))->rc_io_pbase) macro
60 #define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_IO_DEV_SIZE - 1)
H A Drmixl_obio_el_space.c59 #define CHIP_W1_SYS_START(v) (((struct rmixl_config *)(v))->rc_io_pbase) macro
60 #define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_IO_DEV_SIZE - 1)
H A Drmixl_pci_cfg_space.c60 (CHIP_W1_SYS_START(v) + \
62 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
H A Drmixl_pci_ecfg_space.c60 (CHIP_W1_SYS_START(v) + \
62 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
H A Drmixl_pci_io_space.c58 #define CHIP_W1_BUS_END(v) (CHIP_W1_SYS_START(v) + \
60 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
H A Drmixl_pci_mem_space.c58 #define CHIP_W1_BUS_END(v) (CHIP_W1_SYS_START(v) + \
60 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
/netbsd-6-1-5-RELEASE/sys/arch/evbmips/malta/
H A Dmalta_bus_mem.c60 #define CHIP_W1_SYS_START(v) ((u_long)MALTA_PCIMEM1_BASE) macro
68 #define CHIP_W1_SYS_START(v) ((u_long)MALTA_PCIMEM1_BASE) macro
H A Dmalta_bus_io.c53 #define CHIP_W1_SYS_START(v) ((u_long)MALTA_PCIMEM3_BASE) macro
/netbsd-6-1-5-RELEASE/sys/arch/mips/adm5120/
H A Dadm5120_obio_space.c81 #define CHIP_W1_SYS_START(v) 0UL macro
H A Dadm5120_pciio_space.c51 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
H A Dadm5120_pcimem_space.c51 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
H A Dadm5120_extio_space.c78 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
/netbsd-6-1-5-RELEASE/sys/arch/mips/alchemy/
H A Dau_cpureg_mem.c52 #define CHIP_W1_SYS_START(v) 0UL macro
/netbsd-6-1-5-RELEASE/sys/arch/mips/atheros/
H A Darbusle.c49 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
/netbsd-6-1-5-RELEASE/sys/arch/mips/sibyte/pci/
H A Dsbbrz_bus_io.c54 #define CHIP_W1_SYS_START(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES + CHIP_W1_BUS_START(v)) macro
H A Dsbbrz_bus_mem.c54 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
/netbsd-6-1-5-RELEASE/sys/arch/algor/algor/
H A Dalgor_p4032_bus_locio.c61 #define CHIP_W1_SYS_START(v) 0 macro
H A Dalgor_p4032_bus_io.c65 #define CHIP_W1_SYS_START(v) P4032_PCIIO macro
H A Dalgor_p5064_bus_io.c61 #define CHIP_W1_SYS_START(v) P5064_PCIIO macro
H A Dalgor_p6032_bus_io.c61 #define CHIP_W1_SYS_START(v) ((u_long)BONITO_PCIIO_BASE) macro
/netbsd-6-1-5-RELEASE/sys/arch/mips/ralink/
H A Dralink_bus.c109 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v) macro
/netbsd-6-1-5-RELEASE/sys/arch/evbmips/gdium/
H A Dgdium_bus_io.c62 #define CHIP_W1_SYS_START(v) ((u_long)BONITO_PCIIO_BASE) macro
H A Dgdium_bus_mem.c67 #define CHIP_W1_SYS_START(v) ((u_long)BONITO_PCILO_BASE) macro
/netbsd-6-1-5-RELEASE/sys/arch/evbmips/loongson/
H A Dloongson_bus_io.c64 #define CHIP_W1_SYS_START(v) ((u_long)BONITO_PCIIO_BASE) macro

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