Searched refs:CHIP_W1_BUS_START (Results 1 - 25 of 32) sorted by relevance

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/netbsd-6-1-5-RELEASE/sys/arch/mips/adm5120/
H A Dadm5120_pciio_space.c49 #define CHIP_W1_BUS_START(v) ADM5120_BASE_PCI_IO macro
51 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
H A Dadm5120_pcimem_space.c49 #define CHIP_W1_BUS_START(v) ADM5120_BASE_PCI_MEM macro
51 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
H A Dadm5120_extio_space.c76 #define CHIP_W1_BUS_START(v) ADM5120_BASE_EXTIO0 macro
78 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
H A Dadm5120_obio_space.c79 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
/netbsd-6-1-5-RELEASE/sys/arch/mips/atheros/
H A Darbusle.c47 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
49 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
/netbsd-6-1-5-RELEASE/sys/arch/mips/sibyte/pci/
H A Dsbbrz_bus_io.c52 #define CHIP_W1_BUS_START(v) 0x00008000UL macro
54 #define CHIP_W1_SYS_START(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES + CHIP_W1_BUS_START(v))
H A Dsbbrz_bus_mem.c52 #define CHIP_W1_BUS_START(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES_32 + 0x01000000) macro
54 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
/netbsd-6-1-5-RELEASE/sys/arch/mips/ralink/
H A Dralink_bus.c107 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
109 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
/netbsd-6-1-5-RELEASE/sys/arch/mips/rmi/
H A Drmixl_pci_cfg_space.c57 #define CHIP_W1_BUS_START(v) \ macro
62 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
H A Drmixl_pci_ecfg_space.c57 #define CHIP_W1_BUS_START(v) \ macro
62 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
H A Drmixl_pci_io_space.c57 #define CHIP_W1_BUS_START(v) (((struct rmixl_config *)(v))->rc_pci_io_pbase) macro
60 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
H A Drmixl_pci_mem_space.c57 #define CHIP_W1_BUS_START(v) (((struct rmixl_config *)(v))->rc_pci_mem_pbase) macro
60 #define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
H A Drmixl_iobus_space.c64 #define CHIP_W1_BUS_START(v) 0 macro
H A Drmixl_obio_eb_space.c57 #define CHIP_W1_BUS_START(v) 0 macro
H A Drmixl_obio_el_space.c57 #define CHIP_W1_BUS_START(v) 0 macro
/netbsd-6-1-5-RELEASE/sys/arch/evbmips/malta/
H A Dmalta_bus_mem.c57 #define CHIP_W1_BUS_START(v) MALTA_PCIMEM1_BASE macro
66 #define CHIP_W1_BUS_START(v) MALTA_PCIMEM1_BASE macro
H A Dmalta_bus_io.c51 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
/netbsd-6-1-5-RELEASE/sys/arch/mips/alchemy/
H A Dau_cpureg_mem.c50 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
/netbsd-6-1-5-RELEASE/sys/arch/algor/algor/
H A Dalgor_p4032_bus_locio.c59 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
H A Dalgor_p4032_bus_io.c61 #define CHIP_W1_BUS_START(v) \ macro
H A Dalgor_p5064_bus_io.c59 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
H A Dalgor_p6032_bus_io.c59 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
/netbsd-6-1-5-RELEASE/sys/arch/evbmips/gdium/
H A Dgdium_bus_io.c60 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
H A Dgdium_bus_mem.c65 #define CHIP_W1_BUS_START(v) 0x00000000UL macro
/netbsd-6-1-5-RELEASE/sys/arch/evbmips/loongson/
H A Dloongson_bus_io.c62 #define CHIP_W1_BUS_START(v) 0x00000000UL macro

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