Searched refs:BIT5 (Results 1 - 11 of 11) sorted by relevance

/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/ppc/
H A Didecode_fields.h92 #define TO_0_ ((TO & BIT5(0)) != 0)
93 #define TO_1_ ((TO & BIT5(1)) != 0)
94 #define TO_2_ ((TO & BIT5(2)) != 0)
95 #define TO_3_ ((TO & BIT5(3)) != 0)
96 #define TO_4_ ((TO & BIT5(4)) != 0)
98 #define BO_0_ ((BO & BIT5(0)) != 0)
99 #define BO_1_ ((BO & BIT5(1)) != 0)
100 #define BO_2_ ((BO & BIT5(2)) != 0)
101 #define BO_3_ ((BO & BIT5(3)) != 0)
102 #define BO_4_ ((BO & BIT5(
[all...]
H A Dbits.h97 #define BIT5(POS) (1 << _MAKE_SHIFT(5, POS)) macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/testsuite/gcc.target/sh/
H A Dsh2a-bld.c22 unsigned char BIT5:1; member in struct:__anon6625::__anon6626::__anon6627
40 USRSTR.ICR0.BIT.BIT5 |= b;
H A Dsh2a-band.c17 unsigned char BIT5:1; member in struct:__anon6620::__anon6621::__anon6622
68 a = USRSTR.ICR0.BIT.BIT5 & USRSTR.ICR0.BIT.BIT7;
73 PORT.BIT.IOR3 = PORT.BIT.IOR2 & USRSTR.ICR0.BIT.BIT5;
78 PORT.BIT.IOR8 = PORT.BIT.IOR14 & USRSTR.ICR0.BIT.BIT5;
82 PORT.BIT.IOR5 &= USRSTR.ICR0.BIT.BIT5;
H A Dsh2a-bor.c17 unsigned char BIT5:1; member in struct:__anon6628::__anon6629::__anon6630
68 a = USRSTR.ICR0.BIT.BIT5 | USRSTR.ICR0.BIT.BIT7;
73 PORT.BIT.IOR3 = PORT.BIT.IOR2 | USRSTR.ICR0.BIT.BIT5;
78 PORT.BIT.IOR8 = PORT.BIT.IOR14 | USRSTR.ICR0.BIT.BIT5;
82 PORT.BIT.IOR5 |= USRSTR.ICR0.BIT.BIT5;
H A Dsh2a-bxor.c17 unsigned char BIT5:1; member in struct:__anon6633::__anon6634::__anon6635
68 a = USRSTR.ICR0.BIT.BIT5 ^ USRSTR.ICR0.BIT.BIT7;
73 PORT.BIT.IOR3 = PORT.BIT.IOR2 ^ USRSTR.ICR0.BIT.BIT5;
78 PORT.BIT.IOR8 = PORT.BIT.IOR14 ^ USRSTR.ICR0.BIT.BIT5;
82 PORT.BIT.IOR5 ^= USRSTR.ICR0.BIT.BIT5;
/netbsd-6-1-5-RELEASE/sys/dev/pci/
H A Dunichromefb.c703 uni_wr_mask(sc, VIACR, CR36, 0, BIT5+BIT4);
709 uni_wr_mask(sc, VIACR, CR36, BIT5+BIT4, BIT5+BIT4);
715 uni_wr_mask(sc, VIASR, SR01, 0, BIT5);
721 uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5);
788 uni_wr_mask(sc, VIACR, CR11, 0x00, BIT4+BIT5+BIT6);
H A Dunichromereg.h57 #define BIT5 0x20 macro
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/common/
H A Dsim-bits.h255 #define BIT5(POS) (1 << _LSB_SHIFT (5, (POS))) macro
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/opcodes/
H A Dsparc-opc.c1659 #define BIT5 (1<<5)
1660 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet },
1661 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet },
1662 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet },
1664 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet },
1666 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
1667 #undef BIT5
1657 #define BIT5 macro
1665 #undef BIT5 macro
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/opcodes/
H A Dsparc-opc.c1659 #define BIT5 (1<<5)
1660 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet },
1661 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet },
1662 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet },
1664 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet },
1666 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
1667 #undef BIT5
1657 #define BIT5 macro
1665 #undef BIT5 macro

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