Searched refs:AR_PHY_PLL_CTL_40 (Results 1 - 5 of 5) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/external/isc/atheros_hal/dist/ar5211/
H A Dar5211phy.h46 #define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */ macro
H A Dar5211_reset.c622 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
637 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
/netbsd-6-1-5-RELEASE/sys/external/isc/atheros_hal/dist/ar5212/
H A Dar5212phy.h141 #define AR_PHY_PLL_CTL_40 0xaa /* 40 MHz */ macro
H A Dar5212_reset.c912 phyPLL = AR_PHY_PLL_CTL_40;
/netbsd-6-1-5-RELEASE/sys/external/isc/atheros_hal/dist/ar5312/
H A Dar5312_reset.c712 phyPLL = AR_PHY_PLL_CTL_40;

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