Searched refs:AR9344_CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV (Results 1 - 2 of 2) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/arch/mips/atheros/
H A Dar9344.c180 AR9344_CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV);
/netbsd-6-1-5-RELEASE/sys/arch/mips/atheros/include/
H A Dar9344reg.h124 #define AR9344_CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV __BITS(10,14) macro

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