| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
| H A D | RegisterCoalescer.h | 62 CoalescerPair(const TargetRegisterInfo &tri) argument
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
69 const TargetRegisterInfo &tri)
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, const TargetRegisterInfo &tri) argument
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| H A D | Spiller.cpp | 59 const TargetRegisterInfo *tri; member in class:__anon10218::SpillerBase
69 tri = mf.getTarget().getRegisterInfo();
137 tri);
150 true, ss, trc, tri);
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| H A D | RegAllocPBQP.cpp | 131 const TargetRegisterInfo *tri; member in class:__anon10190::RegAllocPBQP
197 const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo(); local
204 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) {
219 BitVector regMaskOverlaps(tri->getNumRegs());
237 for (MCRegUnitIterator Units(preg, tri); Units.isValid(); ++Units) {
281 addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri);
298 const TargetRegisterInfo *tri) {
308 if (tri->regsOverlap(preg1, preg2)) {
486 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> "
487 << tri
294 addInterferenceCosts( PBQP::Matrix &costMat, const PBQPRAProblem::AllowedSet &vr1Allowed, const PBQPRAProblem::AllowedSet &vr2Allowed, const TargetRegisterInfo *tri) argument
[all...] |
| H A D | CalcSpillWeights.cpp | 60 const TargetRegisterInfo &tri,
86 return tri.getMatchingSuperReg(hreg, sub, rc);
112 const TargetRegisterInfo &tri = *MF.getTarget().getRegisterInfo(); local
162 unsigned hint = copyHint(mi, li.reg, tri, mri);
59 copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri) argument
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| H A D | BranchFolding.h | 30 const TargetRegisterInfo *tri,
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| H A D | InterferenceCache.cpp | 29 const TargetRegisterInfo *tri) {
32 TRI = tri;
25 init(MachineFunction *mf, LiveIntervalUnion *liuarray, SlotIndexes *indexes, LiveIntervals *lis, const TargetRegisterInfo *tri) argument
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| H A D | LiveRangeEdit.cpp | 146 const TargetRegisterInfo &tri,
149 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
142 rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &tri, bool Late) argument
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| H A D | RegisterCoalescer.cpp | 206 static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) { argument
209 return tri.composeSubRegIndices(a, b);
212 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI, argument
222 DstSub = compose(tri, MI->getOperand(0).getSubReg(),
1293 const TargetRegisterInfo *tri)
1295 Indexes(LIS->getSlotIndexes()), TRI(tri),
1972 const TargetRegisterInfo &tri,
1289 JoinVals(LiveInterval &li, unsigned subIdx, SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp, LiveIntervals *lis, const TargetRegisterInfo *tri) argument
1971 RegistersDefinedFromSameValue(LiveIntervals &li, const TargetRegisterInfo &tri, CoalescerPair &CP, VNInfo *VNI, VNInfo *OtherVNI, SmallVector<MachineInstr*, 8> &DupCopies) argument
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| H A D | BranchFolding.cpp | 177 const TargetRegisterInfo *tri,
184 TRI = tri;
175 OptimizeFunction(MachineFunction &MF, const TargetInstrInfo *tii, const TargetRegisterInfo *tri, MachineModuleInfo *mmi) argument
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.h | 41 const ARMBaseRegisterInfo &tri,
45 TRI(tri), STI(sti), LastMI(0) {}
39 ARMHazardRecognizer(const InstrItineraryData *ItinData, const ARMBaseInstrInfo &tii, const ARMBaseRegisterInfo &tri, const ARMSubtarget &sti, const ScheduleDAG *DAG) argument
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| /macosx-10.9.5/WebCore-7537.78.1/platform/graphics/gpu/ |
| H A D | LoopBlinnLocalTriangulator.cpp | 120 Triangle* tri = getTriangle(i); local
121 if (tri->contains(v)) {
122 Vertex* next = tri->nextVertex(v, sideToFill == LoopBlinnConstants::RightSide);
268 Triangle* tri = getTriangle(i);
269 if (tri->contains(v0) && tri->nextVertex(v0, true) == v1)
271 if (tri->contains(v1) && tri->nextVertex(v1, true) == v0)
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| /macosx-10.9.5/misc_cmds-32/calendar/calendars/hr_HR.ISO8859-2/ |
| H A D | calendar.praznici | 22 01/06 Sveta tri kralja
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| /macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
| H A D | RegAllocPBQP.h | 138 const TargetRegisterInfo *tri);
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| /macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/ |
| H A D | TargetRegisterInfo.h | 891 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
892 : TRI(tri), Reg(reg), SubIdx(subidx) {}
914 PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri) argument
915 : TRI(tri), Unit(unit) {}
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| /macosx-10.9.5/vim-53/runtime/syntax/ |
| H A D | ahdl.vim | 29 syn keyword ahdlIdentifier soft srffe srff tffe tff tri wire x
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| H A D | verilog.vim | 44 syn keyword verilogStatement tranif0 tranif1 tri tri0 tri1 triand
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| H A D | verilogams.vim | 48 syn keyword verilogamsType inout reg tri tri0 tri1 triand trior trireg
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1621 const TargetRegisterInfo *tri,
1625 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
1634 RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF);
1741 const TargetRegisterInfo *tri,
1744 tii, tri, tli),
1737 RegReductionPriorityQueue(MachineFunction &mf, bool tracksrp, bool srcorder, const TargetInstrInfo *tii, const TargetRegisterInfo *tri, const TargetLowering *tli) argument
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| /macosx-10.9.5/emacs-92/emacs/etc/ |
| H A D | fr-drdref.tex | 348 \key{bascule le tri sur le nom/date du r\'epertoire courant}{s}
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| H A D | sk-refcard.tex | 577 Pohyb vo vn�tri uzlov:
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