Searched refs:rn (Results 1 - 25 of 80) sorted by relevance

1234

/macosx-10.9.5/JavaScriptCore-7537.78.1/assembler/
H A DARMv7Assembler.h758 void adc(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
761 ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
763 ASSERT(rn != ARMRegisters::pc);
766 m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADC_imm, rn, rd, imm);
769 void add(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
772 ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
774 ASSERT(rn != ARMRegisters::pc);
777 if (rn == ARMRegisters::sp) {
786 } else if (!((rd | rn) & 8)) {
788 m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_imm_T1, (RegisterID)imm.getUInt3(), rn, r
804 add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
814 add(RegisterID rd, RegisterID rn, RegisterID rm) argument
827 add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
849 add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
859 add_S(RegisterID rd, RegisterID rn, RegisterID rm) argument
867 ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
875 ARM_and(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
883 ARM_and(RegisterID rd, RegisterID rn, RegisterID rm) argument
901 asr(RegisterID rd, RegisterID rn, RegisterID rm) argument
943 cmn(RegisterID rn, ARMThumbImmediate imm) argument
951 cmp(RegisterID rn, ARMThumbImmediate imm) argument
962 cmp(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
969 cmp(RegisterID rn, RegisterID rm) argument
978 eor(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
987 eor(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
996 eor(RegisterID rd, RegisterID rn, RegisterID rm) argument
1027 ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1040 ldrWide8BitImmediate(RegisterID rt, RegisterID rn, uint8_t immediate) argument
1046 ldrCompact(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1065 ldr(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1088 ldr(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1101 ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1123 ldrh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1145 ldrh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1158 ldrb(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1169 ldrb(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1192 ldrb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1204 ldrsb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1216 ldrsh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1236 lsl(RegisterID rd, RegisterID rn, RegisterID rm) argument
1252 lsr(RegisterID rd, RegisterID rn, RegisterID rm) argument
1350 orr(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1358 orr(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1366 orr(RegisterID rd, RegisterID rn, RegisterID rm) argument
1376 orr_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1384 orr_S(RegisterID rd, RegisterID rn, RegisterID rm) argument
1402 ror(RegisterID rd, RegisterID rn, RegisterID rm) argument
1411 sdiv(RegisterID rd, RegisterID rn, RegisterID rm) argument
1420 smull(RegisterID rdLo, RegisterID rdHi, RegisterID rn, RegisterID rm) argument
1431 str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1456 str(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1479 str(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1492 strb(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1515 strb(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1538 strb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1551 strh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1574 strh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1597 strh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1609 sub(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1639 sub(RegisterID rd, ARMThumbImmediate imm, RegisterID rn) argument
1652 sub(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1662 sub(RegisterID rd, RegisterID rn, RegisterID rm) argument
1671 sub_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1696 sub_S(RegisterID rd, ARMThumbImmediate imm, RegisterID rn) argument
1707 sub_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1717 sub_S(RegisterID rd, RegisterID rn, RegisterID rm) argument
1725 tst(RegisterID rn, ARMThumbImmediate imm) argument
1733 tst(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1740 tst(RegisterID rn, RegisterID rm) argument
1748 ubfx(RegisterID rd, RegisterID rn, unsigned lsb, unsigned width) argument
1757 udiv(RegisterID rd, RegisterID rn, RegisterID rm) argument
1766 vadd(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm) argument
1799 vdiv(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm) argument
1804 vldr(FPDoubleRegisterID rd, RegisterID rn, int32_t imm) argument
1809 flds(FPSingleRegisterID rd, RegisterID rn, int32_t imm) argument
1814 vmov(RegisterID rd, FPSingleRegisterID rn) argument
1820 vmov(FPSingleRegisterID rd, RegisterID rn) argument
1826 vmov(RegisterID rd1, RegisterID rd2, FPDoubleRegisterID rn) argument
1840 vmov(FPDoubleRegisterID rd, FPDoubleRegisterID rn) argument
1851 vmul(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm) argument
1856 vstr(FPDoubleRegisterID rd, RegisterID rn, int32_t imm) argument
1861 fsts(FPSingleRegisterID rd, RegisterID rn, int32_t imm) argument
1866 vsub(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm) argument
2752 vfpMemOp(OpcodeID1 op1, OpcodeID2 op2, bool size, RegisterID rn, VFPOperand rd, int32_t imm) argument
[all...]
H A DARMAssembler.h249 void emitInstruction(ARMWord op, int rd, int rn, ARMWord op2) argument
252 m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
271 void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL) argument
273 emitInstruction(toARMWord(cc) | AND, rd, rn, op2);
276 void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL) argument
278 emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2); local
281 void eor(int rd, int rn, ARMWord op2, Condition cc = AL) argument
283 emitInstruction(toARMWord(cc) | EOR, rd, rn, op2);
286 void eors(int rd, int rn, ARMWord op2, Condition cc = AL) argument
288 emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op local
291 sub(int rd, int rn, ARMWord op2, Condition cc = AL) argument
296 subs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
298 emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2); local
301 rsb(int rd, int rn, ARMWord op2, Condition cc = AL) argument
306 rsbs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
308 emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2); local
311 add(int rd, int rn, ARMWord op2, Condition cc = AL) argument
316 adds(int rd, int rn, ARMWord op2, Condition cc = AL) argument
318 emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2); local
321 adc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
326 adcs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
328 emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2); local
331 sbc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
336 sbcs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
338 emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2); local
341 rsc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
346 rscs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
348 emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2); local
351 tst(int rn, ARMWord op2, Condition cc = AL) argument
353 emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2); local
356 teq(int rn, ARMWord op2, Condition cc = AL) argument
358 emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2); local
361 cmp(int rn, ARMWord op2, Condition cc = AL) argument
363 emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2); local
366 cmn(int rn, ARMWord op2, Condition cc = AL) argument
368 emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2); local
371 orr(int rd, int rn, ARMWord op2, Condition cc = AL) argument
376 orrs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
378 emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2); local
405 bic(int rd, int rn, ARMWord op2, Condition cc = AL) argument
410 bics(int rd, int rn, ARMWord op2, Condition cc = AL) argument
412 emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2); local
425 mul(int rd, int rn, int rm, Condition cc = AL) argument
430 muls(int rd, int rn, int rm, Condition cc = AL) argument
435 mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL) argument
520 halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) argument
522 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm); local
530 halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) argument
768 vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn) argument
948 revertBranchPtrWithPatch(void* instructionStart, RegisterID rn, ARMWord imm) argument
[all...]
/macosx-10.9.5/xnu-2422.115.4/bsd/net/
H A Dradix.c113 #define RN_MATCHF(rn, f, arg) (f == NULL || (*f)((rn), arg))
941 struct radix_node *rn, *last; local
965 for (rn = h->rnh_treetop; rn->rn_bit >= 0; ) {
966 last = rn;
967 if (!(rn->rn_bmask & xm[rn->rn_offset]))
970 if (rn->rn_bmask & xa[rn
1063 struct radix_node *rn; local
[all...]
H A Droute.c795 rn_match_ifscope(struct radix_node *rn, void *arg) argument
797 struct rtentry *rt = (struct rtentry *)rn;
1683 struct radix_node *rn; local
1759 if ((rn = rnh->rnh_deladdr(dst, netmask, rnh)) == NULL)
1761 if (rn->rn_flags & (RNF_ACTIVE | RNF_ROOT)) {
1765 rt = (struct rtentry *)rn;
2029 rn = rnh->rnh_addaddr((caddr_t)ndst, (caddr_t)netmask,
2031 if (rn == 0) {
2056 rn = rnh->rnh_addaddr((caddr_t)ndst,
2068 if (rn
2213 rt_fixdelete(struct radix_node *rn, void *vp) argument
2250 rt_fixchange(struct radix_node *rn, void *vp) argument
2678 struct radix_node *rn; local
2752 struct radix_node *rn0, *rn; local
[all...]
/macosx-10.9.5/vim-53/src/
H A Dswis.s4 ar0 rn 0
5 ar1 rn 1
6 ar2 rn 2
7 ar3 rn 3
8 ar4 rn 4
9 ar5 rn 5
10 ar6 rn 6
11 ar7 rn 7
12 ar10 rn 10
13 ar11 rn 1
[all...]
/macosx-10.9.5/OpenSSH-186/osslshim/ossl/
H A Dossl-lhash.c212 LHASH_NODE *nn, **rn; local
220 rn = getrn(lh, data, &hash);
222 if (*rn == NULL) {
232 *rn = nn;
238 ret = (*rn)->data;
239 (*rn)->data = data;
250 LHASH_NODE *nn, **rn; local
254 rn = getrn(lh, data, &hash);
256 if (*rn == NULL) {
260 nn = *rn;
281 LHASH_NODE **rn; local
[all...]
/macosx-10.9.5/Security-55471.14.18/libsecurity_apple_csp/open_ssl/lhash/
H A Dlhash.c200 LHASH_NODE *nn,**rn; local
207 rn=getrn(lh,data,&hash);
209 if (*rn == NULL)
221 *rn=nn;
228 ret= (*rn)->data;
229 (*rn)->data=data;
238 LHASH_NODE *nn,**rn; local
242 rn=getrn(lh,data,&hash);
244 if (*rn == NULL)
251 nn= *rn;
269 LHASH_NODE **rn; local
[all...]
/macosx-10.9.5/cxxfilt-11/cxxfilt/opcodes/
H A Dsh-dis.c34 int rn,
51 fprintf_fn (stream, "@r%d", rn);
58 fprintf_fn (stream, "@r%d+", rn);
62 fprintf_fn (stream, "@r%d+r8", rn);
66 fprintf_fn (stream, "@r%d+r9", rn);
499 int rn = 0; local
637 rn = nibs[n];
645 rn = (nibs[n] & 0xc) >> 2;
648 rn = (nibs[n] & 0xc) >> 2;
656 rn
33 print_movxy(const sh_opcode_info *op, int rn, int rm, fprintf_ftype fprintf_fn, void *stream) argument
[all...]
H A Dh8500-dis.c94 int rn = 0; local
126 rn = buffer[byte] & 0x7;
220 func (stream, "@(0x%x:16,r%d)", disp, rn);
223 func (stream, "@(0x%x:8 (%d),r%d)", disp & 0xff, disp, rn);
239 func (stream, "r%d", rn);
248 func (stream, "@-r%d", rn);
251 func (stream, "@r%d+", rn);
254 func (stream, "@r%d", rn);
H A Dh8300-dis.c191 int rn,
217 outfn (stream, "%s", regnames[rn]);
221 outfn (stream, "%s", wregnames[rn]);
225 outfn (stream, "%s", lregnames[rn]);
235 outfn (stream, "%s.b", regnames[rn < 8 ? rn + 8 : rn]);
240 outfn (stream, "%s.w", wregnames[rn < 8 ? rn : rn
185 print_one_arg(disassemble_info *info, bfd_vma addr, op_type x, int cst, int cstlen, int rdisp_n, int rn, const char **pregnames, int len) argument
[all...]
/macosx-10.9.5/JavaScriptCore-7537.78.1/disassembler/ARMv7/
H A DARMv7DOpcode.cpp358 appendRegisterName(rn());
370 appendRegisterName(rn());
424 appendRegisterName(rn());
434 appendRegisterName(rn());
444 appendRegisterName(rn());
506 appendRegisterName(rn());
526 appendRegisterName(rn());
795 if (rn() == 15) {
844 appendRegisterName(rn());
856 appendRegisterName(rn());
[all...]
H A DARMv7DOpcode.h262 unsigned rn() { return (m_opcode >> 3) & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractT1
279 unsigned rn() { return (m_opcode >> 3) & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate3
350 unsigned rn() { return (m_opcode >> 8) & 0x3; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeCompareImmediateT1
364 unsigned rn() { return m_opcode & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT1
377 unsigned rn() { return ((m_opcode >> 4) & 0x8) | (m_opcode & 0x7); } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT2
442 unsigned rn() { return (m_opcode >> 3) & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate
480 unsigned rn() { return (m_opcode >> 3) & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterOffsetT1
578 unsigned rn() { return m_opcode & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeMiscCompareAndBranch
712 unsigned rn() { return (m_opcode >> 16) & 0xf; } function in class:JSC::ARMv7Disassembler::ARMv7D32BitOpcode
/macosx-10.9.5/swig-10/Source/Swig/
H A Dnaming.c418 DOH *rn = 0; local
422 rn = Getattr(n, decl);
424 rn = Getattr(n, "start");
426 return rn;
431 DOH *rn = 0; local
434 rn = get_object(n, decl);
435 if ((!rn) && ncdecl)
436 rn = get_object(n, ncdecl);
437 if (!rn)
438 rn
445 DOH *rn = 0; local
1187 Swig_name_match_nameobj(Hash *rn, Node *n) argument
1241 Hash *rn = Getitem(namelist, i); local
1483 Hash *rn = Swig_name_object_get(Swig_name_rename_hash(), prefix, name, decl); local
[all...]
/macosx-10.9.5/xnu-2422.115.4/bsd/netinet/
H A Din_rmx.c253 struct radix_node *rn; local
257 rn = rn_delete(v_arg, netmask_arg, head);
258 if (rt_verbose > 1 && rn != NULL) {
260 struct rtentry *rt = (struct rtentry *)rn;
269 return (rn);
276 in_validate(struct radix_node *rn) argument
278 struct rtentry *rt = (struct rtentry *)rn;
304 return (rn);
325 struct radix_node *rn = rn_match_args(v_arg, head, f, w); local
327 if (rn !
358 in_clsroute(struct radix_node *rn, struct radix_node_head *head) argument
458 in_rtqkill(struct radix_node *rn, void *rock) argument
707 in_ifadownkill(struct radix_node *rn, void *xap) argument
[all...]
/macosx-10.9.5/xnu-2422.115.4/bsd/netinet6/
H A Din6_rmx.c335 struct radix_node *rn; local
339 rn = rn_delete(v_arg, netmask_arg, head);
340 if (rn != NULL) {
341 struct rtentry *rt = (struct rtentry *)rn;
357 return (rn);
364 in6_validate(struct radix_node *rn) argument
366 struct rtentry *rt = (struct rtentry *)rn;
392 return (rn);
413 struct radix_node *rn = rn_match_args(v_arg, head, f, w); local
415 if (rn !
445 in6_clsroute(struct radix_node *rn, struct radix_node_head *head) argument
547 in6_rtqkill(struct radix_node *rn, void *rock) argument
[all...]
/macosx-10.9.5/tcl-102/tcl_ext/mk4tcl/metakit/examples/
H A Dmillions.py63 rn = self.recnos
64 if not rn: return 0
65 return rn[-1]+len(self.view[-1].data)
105 rn = self.recnos
106 pos = self.bisect(rn, idx)-1
107 base = rn[pos]
/macosx-10.9.5/file-46/file/src/
H A Dcompress.c148 size_t rn = n; local
162 return rn;
176 size_t rn = n; local
211 rn = n;
223 return rn - n;
230 return rn;
/macosx-10.9.5/ICU-511.35/icuSources/i18n/
H A Duspoof_wsconf.cpp319 for (int32_t rn=0; rn<ignoreSet.getRangeCount(); rn++) {
320 UChar32 rangeStart = ignoreSet.getRangeStart(rn);
321 UChar32 rangeEnd = ignoreSet.getRangeEnd(rn);
/macosx-10.9.5/emacs-92/emacs/src/
H A Dfringe.c915 int y = 0, rn;
927 for (y = 0, rn = 0, row = w->current_matrix->rows;
928 y < yb && rn < nrows;
929 y += row->height, ++row, ++rn)
954 int rn, nrows = w->current_matrix->nrows;
995 for (y = 0, rn = 0;
996 y < yb && rn < nrows;
997 y += row->height, ++rn)
1002 row = w->desired_matrix->rows + rn;
1004 row = w->current_matrix->rows + rn;
914 int y = 0, rn; local
953 int rn, nrows = w->current_matrix->nrows; local
[all...]
/macosx-10.9.5/tcl-102/tcl_ext/tcllib/tcllib/modules/struct/
H A Dmatrix1.tcl928 for {set r $row; set rn [expr {$r + 1}]} {$rn < $rows} {incr r ; incr rn} {
929 set data($c,$r) $data($c,$rn)
930 if {[info exists rowh($rn)]} {
931 set rowh($r) $rowh($rn)
932 unset rowh($rn)
1323 for {set rn $rows ; set r [expr {$rn - 1}]} {$r >= $firstrow} {incr r -1 ; incr rn
[all...]
H A Dmatrix.tcl1044 for {set r $row; set rn [expr {$r + 1}]} {$rn < $rows} {incr r ; incr rn} {
1045 set data($c,$r) $data($c,$rn)
1046 if {[info exists rowh($rn)]} {
1047 set rowh($r) $rowh($rn)
1048 unset rowh($rn)
1530 for {set rn $rows ; set r [expr {$rn - 1}]} {$r >= $firstrow} {incr r -1 ; incr rn
[all...]
/macosx-10.9.5/xnu-2422.115.4/tools/lldbmacros/
H A Dnet.py699 rn = Cast(rt_tables.rnh_treetop, 'radix_node *')
702 while (rn.rn_bit >= 0):
703 rn = rn.rn_u.rn_node.rn_L
706 base = Cast(rn, 'radix_node *')
707 while ((rn.rn_parent.rn_u.rn_node.rn_R == rn) and (rn.rn_flags & RNF_ROOT == 0)):
708 rn = rn
[all...]
/macosx-10.9.5/tcl-102/tcl_ext/tcllib/tcllib/modules/math/
H A Dpdf_stat.tcl789 set rn $p
791 set rn [expr {$rn + 1.0}]
792 set term [expr {1.0 * $term * $x/$rn}]
816 set rn [expr {1.0 * $pn5/$pn6}]
817 set dif [expr {abs($gin - $rn)}]
818 if {$dif <= $tol && $dif <= $tol * $rn} {
821 set gin $rn
/macosx-10.9.5/vim-53/runtime/ftplugin/
H A Dperl6.vim6 " Contributors: Hinrik ��rn Sigur��sson <hinrik.sig@gmail.com>
/macosx-10.9.5/vim-53/runtime/macros/hanoi/
H A Dhanoi.vim60 map R $rn

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