Searched refs:Subtarget (Results 1 - 25 of 98) sorted by relevance

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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DARMTargetMachine.cpp46 Subtarget(TT, CPU, FS),
48 InstrItins(Subtarget.getInstrItineraryData()) {
62 InstrInfo(Subtarget),
63 DataLayout(Subtarget.isAPCS_ABI() ?
66 Subtarget.isAAPCS_ABI() ?
74 FrameLowering(Subtarget) {
75 if (!Subtarget.hasARMOps())
76 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
88 InstrInfo(Subtarget.hasThumb2()
89 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
147 const ARMSubtarget *Subtarget = &getARMSubtarget(); local
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H A DARMAsmPrinter.h35 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
37 const ARMSubtarget *Subtarget; member in class:llvm::ARMAsmPrinter
53 Subtarget = &TM.getSubtarget<ARMSubtarget>();
111 if (!Subtarget->isTargetDarwin())
113 return Subtarget->isThumb() ?
H A DARMTargetMachine.h36 ARMSubtarget Subtarget; member in class:llvm::ARMBaseTargetMachine
49 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
95 return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
143 return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86TargetMachine.cpp79 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
80 FrameLowering(*this, Subtarget),
82 InstrItins(Subtarget.getInstrItineraryData()){
86 Subtarget.setPICStyle(PICStyles::None);
87 } else if (Subtarget.is64Bit()) {
89 Subtarget.setPICStyle(PICStyles::RIPRel);
90 } else if (Subtarget.isTargetCygMing()) {
91 Subtarget.setPICStyle(PICStyles::None);
92 } else if (Subtarget.isTargetDarwin()) {
94 Subtarget
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H A DX86AsmPrinter.h30 const X86Subtarget *Subtarget; member in class:llvm::X86AsmPrinter
34 Subtarget = &TM.getSubtarget<X86Subtarget>();
41 const X86Subtarget &getSubtarget() const { return *Subtarget; }
H A DX86SelectionDAGInfo.cpp22 Subtarget(&TM.getSubtarget<X86Subtarget>()),
48 Subtarget->getMaxInlineSizeThreshold()) {
55 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
104 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
133 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
137 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
190 if (!AlwaysInline && SizeVal > Subtarget->getMaxInlineSizeThreshold())
215 AVT = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
223 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
227 Chain = DAG.getCopyToReg(Chain, dl, Subtarget
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsRegisterInfo.cpp46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
57 if (Subtarget.isSingleFloat())
59 else if (!Subtarget.hasMips64())
61 else if (Subtarget.isABI_N32())
64 assert(Subtarget.isABI_N64());
70 if (Subtarget.isSingleFloat())
72 else if (!Subtarget.hasMips64())
74 else if (Subtarget.isABI_N32())
77 assert(Subtarget.isABI_N64());
97 if (Subtarget
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H A DMipsRegisterInfo.h29 const MipsSubtarget &Subtarget; member in class:llvm::MipsRegisterInfo
32 MipsRegisterInfo(const MipsSubtarget &Subtarget);
H A DMips16RegisterInfo.h24 Mips16RegisterInfo(const MipsSubtarget &Subtarget);
H A DMipsSERegisterInfo.h27 MipsSERegisterInfo(const MipsSubtarget &Subtarget,
H A DMipsSERegisterInfo.cpp60 unsigned SP = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
95 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
118 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
119 unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
H A DMipsTargetMachine.cpp45 Subtarget(TT, CPU, FS, isLittle, RM),
47 (Subtarget.isABI_N64() ?
50 (Subtarget.isABI_N64() ?
54 FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUTargetMachine.cpp40 Subtarget(TT, CPU, FS),
41 DataLayout(Subtarget.getTargetDataString()),
43 FrameLowering(Subtarget),
46 InstrItins(Subtarget.getInstrItineraryData()) {
H A DSPUFrameLowering.h26 const SPUSubtarget &Subtarget; member in class:llvm::SPUFrameLowering
H A DSPUTargetMachine.h30 SPUSubtarget Subtarget; member in class:llvm::SPUTargetMachine
45 return &Subtarget;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp42 Subtarget(TT, CPU, FS, is64Bit),
43 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
44 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
46 InstrItins(Subtarget.getInstrItineraryData()) {
49 if (Subtarget.isBGP())
122 Subtarget.SetJITMode();
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/
H A DMBlazeRegisterInfo.h39 const MBlazeSubtarget &Subtarget; member in struct:llvm::MBlazeRegisterInfo
42 MBlazeRegisterInfo(const MBlazeSubtarget &Subtarget,
H A DMBlazeTargetMachine.cpp40 Subtarget(TT, CPU, FS),
43 FrameLowering(Subtarget),
45 InstrItins(Subtarget.getInstrItineraryData()) {
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430TargetMachine.cpp35 Subtarget(TT, CPU, FS),
39 FrameLowering(Subtarget) { }
H A DMSP430TargetMachine.h33 MSP430Subtarget Subtarget; member in class:llvm::MSP430TargetMachine
51 virtual const MSP430Subtarget *getSubtargetImpl() const { return &Subtarget; }
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/
H A DXCoreTargetMachine.cpp29 Subtarget(TT, CPU, FS),
33 FrameLowering(Subtarget),
H A DXCoreTargetMachine.h28 XCoreSubtarget Subtarget; member in class:llvm::XCoreTargetMachine
44 virtual const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; }
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/
H A DSparcTargetMachine.cpp35 Subtarget(TT, CPU, FS, is64bit),
36 DataLayout(Subtarget.getDataLayout()),
37 InstrInfo(Subtarget),
39 FrameLowering(Subtarget) {
H A DSparcRegisterInfo.h29 SparcSubtarget &Subtarget; member in struct:llvm::SparcRegisterInfo
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonTargetMachine.cpp74 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
76 FrameLowering(Subtarget),
77 InstrItins(&Subtarget.getInstrItineraryData()) {

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