Searched refs:SrcReg (Results 1 - 25 of 69) sorted by relevance

123

/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DPHIEliminationUtils.h17 /// SrcReg when following the CFG edge to SuccMBB. This needs to be after
18 /// any def of SrcReg, but before any subsequent point where control flow
22 unsigned SrcReg);
H A DRegisterCoalescer.h35 /// SrcReg - the virtual register that will be coalesced into dstReg.
36 unsigned SrcReg; member in class:llvm::CoalescerPair
42 /// SrcIdx - The sub-register index of the old SrcReg in the new coalesced
52 /// Flipped - True when DstReg and SrcReg are reversed from the original
58 /// SrcReg and DstReg.
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
105 unsigned getSrcReg() const { return SrcReg; }
111 /// getSrcIdx - Return the subregister index that SrcReg wil
[all...]
H A DPHIEliminationUtils.cpp17 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
19 // SrcReg, but before any subsequent point where control flow might jump out of
23 unsigned SrcReg) {
37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg),
22 findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB, unsigned SrcReg) argument
H A DPHIElimination.cpp295 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); local
298 isImplicitlyDefined(SrcReg, MRI);
299 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
315 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
327 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
333 .addReg(SrcReg, 0, SrcSubReg);
352 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
356 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
366 if (Term->readsRegister(SrcReg))
380 if (KillInst->readsRegister(SrcReg))
[all...]
H A DStrongPHIElimination.cpp249 unsigned SrcReg = SrcMO.getReg(); local
250 addReg(SrcReg);
251 unionRegs(DestReg, SrcReg);
253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
291 unsigned SrcReg = BBI->getOperand(i).getReg(); local
292 addReg(SrcReg);
293 unionRegs(DestReg, SrcReg);
308 unsigned SrcReg = PHI->getOperand(1).getReg(); local
309 unsigned SrcColor = getRegColor(SrcReg);
312 NewReg = SrcReg;
322 unsigned SrcReg = PHI->getOperand(i).getReg(); local
371 unsigned SrcReg = I->second; local
662 unsigned SrcReg = SrcMO.getReg(); local
[all...]
H A DTwoAddressInstructionPass.cpp333 unsigned &SrcReg, unsigned &DstReg,
335 SrcReg = 0;
339 SrcReg = MI.getOperand(1).getReg();
342 SrcReg = MI.getOperand(2).getReg();
346 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
382 unsigned SrcReg, DstReg; local
385 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
387 Reg = SrcReg;
424 unsigned SrcReg; local
426 if (isCopyToReg(UseMI, TII, SrcReg, DstRe
332 isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys) argument
698 unsigned SrcReg, DstReg; local
1214 unsigned SrcReg = SrcMO.getReg(); local
1426 unsigned SrcReg = mi->getOperand(SrcIdx).getReg(); local
1475 UpdateRegSequenceSrcs(unsigned SrcReg, unsigned DstReg, unsigned SubIdx, MachineRegisterInfo *MRI, const TargetRegisterInfo &TRI) argument
1531 unsigned SrcReg = Srcs[i]; local
1680 unsigned SrcReg = MI->getOperand(i).getReg(); local
1746 unsigned SrcReg = MI->getOperand(i).getReg(); local
[all...]
H A DOptimizePHIs.cpp99 unsigned SrcReg = MI->getOperand(i).getReg(); local
100 if (SrcReg == DstReg)
102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
120 SingleValReg = SrcReg;
H A DPeepholeOptimizer.cpp144 unsigned SrcReg, DstReg, SubIdx; local
145 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
149 TargetRegisterInfo::isPhysicalRegister(SrcReg))
152 if (MRI->hasOneNonDBGUse(SrcReg))
163 // The ext instr may be operating on a sub-register of SrcReg as well.
166 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
167 // SrcReg:SubIdx should be replaced.
169 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
187 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end();
199 // Only accept uses of SrcReg
375 unsigned SrcReg, SrcReg2; local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp38 unsigned DestReg, unsigned SrcReg,
41 NVPTX::Int32RegsRegClass.contains(SrcReg))
43 .addReg(SrcReg, getKillRegState(KillSrc));
45 NVPTX::Int8RegsRegClass.contains(SrcReg))
47 .addReg(SrcReg, getKillRegState(KillSrc));
49 NVPTX::Int1RegsRegClass.contains(SrcReg))
51 .addReg(SrcReg, getKillRegState(KillSrc));
53 NVPTX::Float32RegsRegClass.contains(SrcReg))
55 .addReg(SrcReg, getKillRegState(KillSrc));
57 NVPTX::Int16RegsRegClass.contains(SrcReg))
36 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
113 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DestReg) const argument
[all...]
H A DNVPTXInstrInfo.h45 * unsigned SrcReg, bool isKill, int FrameIndex,
55 unsigned DestReg, unsigned SrcReg,
58 unsigned &SrcReg,
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DThumb1InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg,
46 .addReg(SrcReg, getKillRegState(KillSrc)));
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
53 unsigned SrcReg, bool isKill, int FI,
57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
58 isARMLowRegister(SrcReg))) && "Unknown regclass!");
61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
62 isARMLowRegister(SrcReg))) {
74 .addReg(SrcReg, getKillRegState(isKill))
41 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb1InstrInfo.h44 unsigned DestReg, unsigned SrcReg,
48 unsigned SrcReg, bool isKill, int FrameIndex,
H A DThumb2InstrInfo.h45 unsigned DestReg, unsigned SrcReg,
50 unsigned SrcReg, bool isKill, int FrameIndex,
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp87 unsigned &SrcReg, unsigned &DstReg,
93 SrcReg = MI.getOperand(1).getReg();
415 unsigned DestReg, unsigned SrcReg,
418 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
420 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
422 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
424 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
426 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
428 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
436 .addReg(SrcReg)
86 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument
413 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
443 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
587 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
H A DPPCInstrInfo.h72 unsigned SrcReg, bool isKill, int FrameIdx,
96 unsigned &SrcReg, unsigned &DstReg,
123 unsigned DestReg, unsigned SrcReg,
128 unsigned SrcReg, bool isKill, int FrameIndex,
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonPeephole.cpp134 unsigned SrcReg = Src.getReg(); local
137 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
141 PeepholeMap[DstReg] = SrcReg;
158 unsigned SrcReg = Src1.getReg(); local
160 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
170 unsigned SrcReg = Src.getReg(); local
173 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
177 PeepholeMap[DstReg] = SrcReg;
193 unsigned SrcReg = Src.getReg(); local
195 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp87 unsigned DestReg, unsigned SrcReg,
92 if (Mips::CPURegsRegClass.contains(SrcReg))
94 else if (Mips::CCRRegClass.contains(SrcReg))
96 else if (Mips::FGR32RegClass.contains(SrcReg))
98 else if (SrcReg == Mips::HI)
99 Opc = Mips::MFHI, SrcReg = 0;
100 else if (SrcReg == Mips::LO)
101 Opc = Mips::MFLO, SrcReg = 0;
103 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
85 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
155 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
329 unsigned SrcReg = I->getOperand(1).getReg(); local
[all...]
H A DMips16InstrInfo.cpp59 unsigned DestReg, unsigned SrcReg,
64 if (Mips::CPURegsRegClass.contains(SrcReg))
78 if (SrcReg)
79 MIB.addReg(SrcReg, getKillRegState(KillSrc));
84 unsigned SrcReg, bool isKill, int FI,
94 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
57 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
83 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DMips16InstrInfo.h48 unsigned DestReg, unsigned SrcReg,
53 unsigned SrcReg, bool isKill, int FrameIndex,
H A DMipsSEInstrInfo.h49 unsigned DestReg, unsigned SrcReg,
54 unsigned SrcReg, bool isKill, int FrameIndex,
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUInstrInfo.h49 unsigned DestReg, unsigned SrcReg,
55 unsigned SrcReg, bool isKill, int FrameIndex,
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430InstrInfo.h56 unsigned DestReg, unsigned SrcReg,
61 unsigned SrcReg, bool isKill,
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/
H A DSparcInstrInfo.h87 unsigned DestReg, unsigned SrcReg,
92 unsigned SrcReg, bool isKill, int FrameIndex,
H A DSparcInstrInfo.cpp282 unsigned DestReg, unsigned SrcReg,
284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
286 .addReg(SrcReg, getKillRegState(KillSrc));
287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
289 .addReg(SrcReg, getKillRegState(KillSrc));
290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
292 .addReg(SrcReg, getKillRegState(KillSrc));
299 unsigned SrcReg, bool isKill, int FI,
305 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
308 .addReg(SrcReg, getKillRegStat
280 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
298 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/
H A DXCoreInstrInfo.h66 unsigned DestReg, unsigned SrcReg,
71 unsigned SrcReg, bool isKill, int FrameIndex,

Completed in 206 milliseconds

123