Searched refs:Shr (Results 1 - 6 of 6) sorted by relevance
| /macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/ |
| H A D | MCExpr.h | 331 Shr, ///< Shift right (arithmetic or logical, depending on target) enumerator in enum:llvm::MCBinaryExpr::Opcode
411 return Create(Shr, LHS, RHS, Ctx);
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 930 Instruction *InstCombiner::FoldICmpShrCst(ICmpInst &ICI, BinaryOperator *Shr, argument
945 if (ICI.isSigned() != (Shr->getOpcode() == Instruction::AShr))
951 if (Shr->getOpcode() == Instruction::AShr &&
952 (!Shr->isExact() || ShAmtVal == TypeBits - 1))
956 Worklist.Add(Shr);
959 ConstantInt::get(Shr->getType(), APInt::getOneBitSet(TypeBits, ShAmtVal));
962 Shr->getOpcode() == Instruction::AShr ?
963 Builder->CreateSDiv(Shr->getOperand(0), DivCst, "", Shr->isExact()) :
964 Builder->CreateUDiv(Shr
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/MC/ |
| H A D | MCExpr.cpp | 121 case MCBinaryExpr::Shr: OS << ">>"; break;
583 case MCBinaryExpr::Shr: Result = LHS >> RHS; break;
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2198 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2201 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
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| H A D | DAGCombiner.cpp | 9223 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); local
9225 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/MC/MCParser/ |
| H A D | AsmParser.cpp | 1023 Kind = MCBinaryExpr::Shr;
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