| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 370 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, local
373 if (ResultReg == 0) return false;
376 UpdateValueMap(I, ResultReg);
406 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, local
408 if (ResultReg == 0) return false;
411 UpdateValueMap(I, ResultReg);
417 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), local
419 if (ResultReg != 0) {
421 UpdateValueMap(I, ResultReg);
434 unsigned ResultReg local
672 unsigned ResultReg = getRegForValue(ResCI); local
718 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), local
757 unsigned ResultReg = 0; local
863 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), local
917 unsigned ResultReg; local
1144 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); local
1166 unsigned ResultReg = createResultReg(RC); local
1176 unsigned ResultReg = createResultReg(RC); local
1196 unsigned ResultReg = createResultReg(RC); local
1218 unsigned ResultReg = createResultReg(RC); local
1241 unsigned ResultReg = createResultReg(RC); local
1262 unsigned ResultReg = createResultReg(RC); local
1285 unsigned ResultReg = createResultReg(RC); local
1307 unsigned ResultReg = createResultReg(RC); local
1331 unsigned ResultReg = createResultReg(RC); local
1353 unsigned ResultReg = createResultReg(RC); local
1369 unsigned ResultReg = createResultReg(RC); local
1386 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); local
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 89 unsigned &ResultReg);
179 unsigned &ResultReg) {
226 ResultReg = createResultReg(RC);
228 DL, TII.get(Opc), ResultReg), AM);
326 unsigned &ResultReg) {
331 ResultReg = RR;
846 unsigned ResultReg = 0; local
847 if (X86FastEmitLoad(VT, AM, ResultReg)) {
848 UpdateValueMap(I, ResultReg);
931 unsigned ResultReg local
178 X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &ResultReg) argument
324 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
1011 unsigned ResultReg = getRegForValue(I->getOperand(0)); local
1223 unsigned ResultReg = createResultReg(RC); local
1262 unsigned ResultReg = createResultReg(RC); local
1277 unsigned ResultReg = createResultReg(&X86::FR64RegClass); local
1296 unsigned ResultReg = createResultReg(&X86::FR32RegClass); local
1343 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, local
1505 unsigned ResultReg = FuncInfo.CreateRegs(I.getType()); local
1929 unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); local
2093 unsigned ResultReg = createResultReg(RC); local
2124 unsigned ResultReg = createResultReg(RC); local
2148 unsigned ResultReg = createResultReg(RC); local
2187 unsigned ResultReg = createResultReg(RC); local
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 181 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
293 unsigned ResultReg = createResultReg(RC); local
296 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
297 return ResultReg;
303 unsigned ResultReg = createResultReg(RC); local
307 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
313 TII.get(TargetOpcode::COPY), ResultReg)
316 return ResultReg;
323 unsigned ResultReg = createResultReg(RC); local
327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
346 unsigned ResultReg = createResultReg(RC); local
370 unsigned ResultReg = createResultReg(RC); local
392 unsigned ResultReg = createResultReg(RC); local
415 unsigned ResultReg = createResultReg(RC); local
438 unsigned ResultReg = createResultReg(RC); local
457 unsigned ResultReg = createResultReg(RC); local
477 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); local
747 unsigned ResultReg = createResultReg(RC); local
932 unsigned ResultReg = createResultReg(RC); local
1000 ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment, bool isZExt, bool allocReg) argument
1117 unsigned ResultReg; local
1617 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); local
1644 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); local
1707 unsigned ResultReg = createResultReg(RC); local
1798 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32)); local
1838 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
2053 unsigned ResultReg = createResultReg(DstRC); local
2074 unsigned ResultReg = createResultReg(DstRC); local
2437 unsigned ResultReg; local
2603 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32)); local
2630 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); local
2672 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32)); local
2801 unsigned ResultReg = MI->getOperand(0).getReg(); local
[all...] |