| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
| H A D | AllocationOrder.h | 37 /// @param RegClassInfo Information about reserved and allocatable registers.
40 const RegisterClassInfo &RegClassInfo);
|
| H A D | AllocationOrder.cpp | 27 const RegisterClassInfo &RegClassInfo)
28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
25 AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo) argument
|
| H A D | RegAllocBase.h | 66 RegisterClassInfo RegClassInfo; member in class:llvm::RegAllocBase
|
| H A D | RegAllocBase.cpp | 62 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
122 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
|
| H A D | CriticalAntiDepBreaker.h | 39 const RegisterClassInfo &RegClassInfo; member in class:llvm::CriticalAntiDepBreaker
|
| H A D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; member in class:llvm::AggressiveAntiDepBreaker
|
| H A D | PostRASchedulerList.cpp | 82 RegisterClassInfo RegClassInfo; member in class:__anon10179::PostRAScheduler
262 RegClassInfo.runOnMachineFunction(Fn);
291 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
|
| H A D | MachineScheduler.cpp | 58 RegClassInfo = new RegisterClassInfo();
62 delete RegClassInfo;
189 RegClassInfo->runOnMachineFunction(*MF);
400 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
401 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
495 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
|
| H A D | RegAllocBasic.cpp | 229 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
|
| H A D | RegAllocGreedy.cpp | 555 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
556 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
651 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
971 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1238 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1289 if (!RegClassInfo.isProperSubClass(MRI->getRegClass(VirtReg.reg)))
1695 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
|
| H A D | CriticalAntiDepBreaker.cpp | 35 RegClassInfo(RCI),
381 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
|
| H A D | RegAllocFast.cpp | 60 RegisterClassInfo RegClassInfo; member in class:__anon10184::RAFast
528 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
1120 RegClassInfo.runOnMachineFunction(Fn);
|
| H A D | AggressiveAntiDepBreaker.cpp | 124 RegClassInfo(RCI),
619 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
|
| H A D | RegisterCoalescer.cpp | 88 RegisterClassInfo RegClassInfo; member in class:__anon10191::RegisterCoalescer
1053 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
2379 RegClassInfo.runOnMachineFunction(fn);
|
| /macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
| H A D | MachineScheduler.h | 57 RegisterClassInfo *RegClassInfo; member in struct:llvm::MachineSchedContext
198 RegisterClassInfo *RegClassInfo; member in class:llvm::ScheduleDAGMI
234 AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
|