/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/ |
H A D | SparcMachineFunctionInfo.h | 38 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument 44 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument 46 VRegInfo[Reg].first = RC; 50 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument 53 const TargetRegisterClass *OldRC = getRegClass(Reg); 61 setRegClass(Reg, NewRC); 66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument 68 const TargetRegisterClass *OldRC = getRegClass(Reg); 76 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 90 setRegClass(Reg, NewRC); 104 unsigned Reg local [all...] |
H A D | DeadMachineInstructionElim.cpp | 69 unsigned Reg = MO.getReg(); local 70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) 75 if (!MRI->use_nodbg_empty(Reg)) 106 unsigned Reg = *LOI; local 107 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 108 LivePhysRegs.set(Reg); 136 unsigned Reg = MO.getReg(); local 137 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 164 unsigned Reg = MO.getReg(); local 183 unsigned Reg = MO.getReg(); local [all...] |
H A D | AggressiveAntiDepBreaker.cpp | 61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument 62 unsigned Node = GroupNodeIndices[Reg]; 74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { 75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) 76 Regs.push_back(Reg); 83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!"); 96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument 107 IsLive(unsigned Reg) argument 161 unsigned Reg = *AI; local 177 unsigned Reg = *AI; local 190 unsigned Reg = *I; local [all...] |
H A D | AllocationOrder.h | 56 unsigned Reg = *Pos++; local 57 if (Reg != Hint) 58 return Reg;
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H A D | MachineInstrBundle.cpp | 131 unsigned Reg = MO.getReg(); local 132 if (!Reg) 134 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 135 if (LocalDefSet.count(Reg)) { 139 KilledDefSet.insert(Reg); 141 if (ExternUseSet.insert(Reg)) { 142 ExternUses.push_back(Reg); 144 UndefUseSet.insert(Reg); 148 KilledUseSet.insert(Reg); 154 unsigned Reg local 186 unsigned Reg = LocalDefs[i]; local 196 unsigned Reg = ExternUses[i]; local 252 analyzeVirtReg(unsigned Reg, SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) argument 281 analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) argument [all...] |
H A D | CriticalAntiDepBreaker.cpp | 66 unsigned Reg = *AI; local 67 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 68 KillIndices[Reg] = BBSize; 69 DefIndices[Reg] = ~0u; 82 unsigned Reg = *AI; local 83 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 84 KillIndices[Reg] = BBSize; 85 DefIndices[Reg] = ~0u; 97 unsigned Reg = *AI; local 98 Classes[Reg] 188 unsigned Reg = MO.getReg(); local 251 unsigned Reg = MO.getReg(); local 282 unsigned Reg = MO.getReg(); local 581 unsigned Reg = MO.getReg(); local [all...] |
H A D | LiveVariables.cpp | 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { argument 183 VarInfo &VRInfo = getVarInfo(Reg); 192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, argument 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 219 if (TRI->isSubRegister(Reg, DefReg)) { 231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { argument 232 MachineInstr *LastDef = PhysRegDef[Reg]; 234 if (!LastDef && !PhysRegUse[Reg]) { 242 // All of the sub-registers must have been defined before the use of Reg! 244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg 281 FindLastRefOrPartRef(unsigned Reg) argument 311 HandlePhysRegKill(unsigned Reg, MachineInstr *MI) argument 443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVector<unsigned, 4> &Defs) argument 489 unsigned Reg = Defs.back(); local 675 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 700 replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI) argument 713 unsigned Reg = MO.getReg(); local 738 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument 756 isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) argument 837 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local [all...] |
H A D | RegisterPressure.cpp | 272 /// Return true if Reg aliases a register in Regs SparseSet. 273 static bool hasRegAlias(unsigned Reg, SparseSet<unsigned> &Regs, argument 275 assert(!TargetRegisterInfo::isVirtualRegister(Reg) && "only for physregs"); 276 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 282 /// Return true if Reg aliases a register in unsorted Regs SmallVector. 285 findRegAlias(unsigned Reg, SmallVectorImpl<unsigned> &Regs, argument 287 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 296 /// Return true if Reg can be inserted into Regs SmallVector. For virtual 299 findReg(unsigned Reg, bool isVReg, SmallVectorImpl<unsigned> &Regs, argument 302 return std::find(Regs.begin(), Regs.end(), Reg); 353 unsigned Reg = PhysRegOpers.DeadDefs[i-1]; local 376 discoverPhysLiveIn(unsigned Reg) argument 387 discoverPhysLiveOut(unsigned Reg) argument 398 discoverVirtLiveIn(unsigned Reg) argument 410 discoverVirtLiveOut(unsigned Reg) argument 465 unsigned Reg = PhysRegOpers.Defs[i]; local 472 unsigned Reg = VirtRegOpers.Defs[i]; local 481 unsigned Reg = PhysRegOpers.Uses[i]; local 488 unsigned Reg = VirtRegOpers.Uses[i]; local 531 unsigned Reg = PhysRegOpers.Uses[i]; local 541 unsigned Reg = VirtRegOpers.Uses[i]; local 559 unsigned Reg = PhysRegOpers.Defs[i]; local 566 unsigned Reg = VirtRegOpers.Defs[i]; local 684 unsigned Reg = PhysRegOpers.Uses[i]; local 689 unsigned Reg = VirtRegOpers.Uses[i]; local 730 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument 763 unsigned Reg = VirtRegOpers.Uses[i]; local [all...] |
H A D | RegisterScavenging.cpp | 37 void RegScavenger::setUsed(unsigned Reg) { argument 38 RegsAvailable.reset(Reg); 40 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 44 bool RegScavenger::isAliasUsed(unsigned Reg) const { 45 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 109 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { argument 110 BV.set(Reg); 111 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 151 unsigned Reg = MO.getReg(); local 152 if (!Reg || isReserve 176 unsigned Reg = MO.getReg(); local [all...] |
H A D | AggressiveAntiDepBreaker.h | 91 unsigned GetGroup(unsigned Reg); 109 unsigned LeaveGroup(unsigned Reg); 111 /// IsLive - Return true if Reg is live 112 bool IsLive(unsigned Reg); 171 void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag, 177 BitVector GetRenameRegisters(unsigned Reg);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.h | 74 bool isAllocated(unsigned Reg) const { 75 return UsedRegs[Reg/32] & (1 << (Reg&31)); 121 unsigned AllocateReg(unsigned Reg) { argument 122 if (isAllocated(Reg)) return 0; 123 MarkAllocated(Reg); 124 return Reg; 128 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument 129 if (isAllocated(Reg)) return 0; 130 MarkAllocated(Reg); 144 unsigned Reg = Regs[FirstUnalloc]; local 157 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/MC/ |
H A D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument 20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers) 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) 26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument 31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; 32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { 42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; 43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 77 return MO->Contents.Reg.Next; 185 /// Reg are Debug instructions. 264 MachineInstr *getVRegDef(unsigned Reg) const; 269 MachineInstr *getUniqueVRegDef(unsigned Reg) const; 275 void clearKillFlags(unsigned Reg) const; 292 const TargetRegisterClass *getRegClass(unsigned Reg) const { 293 return VRegInfo[Reg].first; 298 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 307 const TargetRegisterClass *constrainRegClass(unsigned Reg, 311 /// recomputeRegClass - Try to find a legal super-class of Reg' 335 setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) argument 378 setPhysRegUsed(unsigned Reg) argument 392 setPhysRegUnused(unsigned Reg) argument 462 addLiveIn(unsigned Reg, unsigned vreg = 0) argument 465 addLiveOut(unsigned Reg) argument [all...] |
H A D | LiveVariables.h | 108 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through 109 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in 112 unsigned Reg, 152 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the 155 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI); 160 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); 161 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI, 167 MachineInstr *FindLastRefOrPartRef(unsigned Reg); 172 MachineInstr *FindLastPartialDef(unsigned Reg, 283 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument 301 isPHIJoin(unsigned Reg) argument 304 setPHIJoin(unsigned Reg) argument [all...] |
H A D | RegisterScavenging.h | 127 void setUsed(unsigned Reg); 130 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); } 134 bool isUsed(unsigned Reg) const { 135 return !RegsAvailable.test(Reg) || isReserved(Reg); 138 /// isAliasUsed - Is Reg or an alias currently in use? 139 bool isAliasUsed(unsigned Reg) const; 150 /// Add Reg and all its sub-registers to BV. 151 void addRegWithSubRegs(BitVector &BV, unsigned Reg); [all...] |
H A D | CallingConvLower.h | 191 bool isAllocated(unsigned Reg) const { 192 return UsedRegs[Reg/32] & (1 << (Reg&31)); 243 unsigned AllocateReg(unsigned Reg) { argument 244 if (isAllocated(Reg)) return 0; 245 MarkAllocated(Reg); 246 return Reg; 250 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument 251 if (isAllocated(Reg)) return 0; 252 MarkAllocated(Reg); 266 unsigned Reg = Regs[FirstUnalloc]; local 279 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local [all...] |
H A D | LiveIntervalAnalysis.h | 106 LiveInterval &getInterval(unsigned Reg) { argument 107 LiveInterval *LI = VirtRegIntervals[Reg]; 112 const LiveInterval &getInterval(unsigned Reg) const { 113 return const_cast<LiveIntervals*>(this)->getInterval(Reg); 116 bool hasInterval(unsigned Reg) const { 117 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; 121 LiveInterval &getOrCreateInterval(unsigned Reg) { argument 122 if (!hasInterval(Reg)) { 123 VirtRegIntervals.grow(Reg); 130 removeInterval(unsigned Reg) argument [all...] |
H A D | FunctionLoweringInfo.h | 151 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { argument 152 if (!LiveOutRegInfo.inBounds(Reg)) 155 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 167 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth); 170 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, argument 176 LiveOutRegInfo.grow(Reg); 177 LiveOutInfo &LOI = LiveOutRegInfo[Reg]; 195 unsigned Reg = It->second; local 196 LiveOutRegInfo.grow(Reg); 197 LiveOutRegInfo[Reg] [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | MLxExpansionPass.cpp | 65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const; 89 unsigned Reg = MI->getOperand(1).getReg(); local 90 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); 99 Reg = DefMI->getOperand(1).getReg(); 100 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 101 DefMI = MRI->getVRegDef(Reg); 105 Reg = DefMI->getOperand(2).getReg(); 106 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 107 DefMI = MRI->getVRegDef(Reg); 117 unsigned Reg = MI->getOperand(0).getReg(); local 143 unsigned Reg = MI->getOperand(1).getReg(); local 184 hasRAWHazard(unsigned Reg, MachineInstr *MI) const argument [all...] |
H A D | ARMBaseRegisterInfo.h | 38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { argument 40 switch (Reg) { 53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { argument 55 switch (Reg) { 64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { argument 66 switch (Reg) { 127 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 130 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 158 bool isLowRegister(unsigned Reg) const; 173 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) cons [all...] |
H A D | ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList, 4)) 35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 49 if (unsigned Reg = State.AllocateReg(RegList, 4)) 50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 78 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); local 79 if (Reg == 0) { 93 if (HiRegList[i] == Reg) 100 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 123 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); local 124 if (Reg [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
H A D | MipsRegisterInfo.cpp | 102 for (RegIter Reg = Mips::AFGR64RegClass.begin(), 103 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) 104 Reserved.set(*Reg); 107 for (RegIter Reg = Mips::CPU64RegsRegClass.begin(), 108 EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg) 109 Reserved.set(*Reg); 111 for (RegIter Reg = Mips::FGR64RegClass.begin(), 112 EReg = Mips::FGR64RegClass.end(); Reg ! [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 75 bool contains(unsigned Reg) const { 76 return MC->contains(Reg); 159 /// For all Reg in SuperRC: 160 /// this->contains(Reg:Idx) 251 /// returns true if Reg is in the range used for stack slots. 257 static bool isStackSlot(unsigned Reg) { argument 258 return int(Reg) >= (1 << 30); 263 static int stackSlot2Index(unsigned Reg) { argument 264 assert(isStackSlot(Reg) && "Not a stack slot"); 265 return int(Reg 277 isPhysicalRegister(unsigned Reg) argument 284 isVirtualRegister(unsigned Reg) argument 291 virtReg2Index(unsigned Reg) argument 888 unsigned Reg; member in class:llvm::TargetRegisterInfo::PrintReg [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 67 bool contains(unsigned Reg) const { 68 unsigned InByte = Reg % 8; 69 unsigned Byte = Reg / 8; 312 unsigned getSubReg(unsigned Reg, unsigned Idx) const; 315 /// Reg so its sub-register of index SubIdx is Reg. 316 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 394 /// MCSubRegIterator enumerates all sub-registers of Reg. 397 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 398 init(Reg, MCR 416 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf) argument 443 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) argument [all...] |