/macosx-10.9.5/cxxfilt-11/cxxfilt/opcodes/ |
H A D | openrisc-opc.c | 152 { { MNEM, ' ', OP (RA), 0 } }, 158 { { MNEM, ' ', OP (RA), 0 } }, 188 { { MNEM, ' ', OP (RA), 0 } }, 212 { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, 218 { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, 224 { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 230 { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 236 { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 242 { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, 248 { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', [all...] |
H A D | ppc-opc.c | 371 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 372 #define RA NSI + 1 376 /* As above, but 0 in the RA field means zero, not r0. */ 377 #define RA0 RA + 1 380 /* The RA field in the DQ form lq instruction, which has special 385 /* The RA field in a D or X form instruction which is an updating 386 load, which means that the RA field may not be zero and may not 391 /* The RA field in an lmw instruction, which has special value 396 /* The RA field in a D or X form instruction which is an updating 397 store or an updating floating point load, which means that the RA 370 #define RA macro [all...] |
H A D | alpha-opc.c | 58 /* The RB field when it is the same as the RA field in the same insn. 60 the RA field into the RB field, and the extraction function just 209 #define RA (UNUSED + 1) 211 #define RB (RA + 1) 241 /* The RB field when it must be the same as the RA field. */ 249 /* The RC field when it can *default* to RA. */ 259 /* The FC field when it can *default* to RA. */ 413 #define ARG_BRA { RA, BDISP } 417 #define ARG_MEM { RA, MDISP, PRB } 419 #define ARG_OPR { RA, R 207 #define RA macro [all...] |
/macosx-10.9.5/cctools-845/otool/ |
H A D | ppc_disasm.c | 44 #define RA(x) (((x) >> 16) & 0x1f) macro 222 if(RA(opcode) == 0) 225 printf("addi\tr%u,r%u,", RT(opcode), RA(opcode)); 232 if(RA(opcode) == 0) 235 printf("addis\tr%u,r%u,", RT(opcode), RA(opcode)); 242 printf("addic\tr%u,r%u,", RT(opcode), RA(opcode)); 249 printf("addic.\tr%u,r%u,", RT(opcode), RA(opcode)); 256 printf("subfic\tr%u,r%u,", RT(opcode), RA(opcode)); 263 printf("mulli\tr%u,r%u,", RT(opcode), RA(opcode)); 272 RA(opcod [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 533 unsigned RA = getRA(insn); local 546 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) 550 instr.addOperand(MCOperand::CreateReg(RA)); 554 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) 557 instr.addOperand(MCOperand::CreateReg(RA)); 562 if (RD == UNSUPPORTED || RA == UNSUPPORTED) 565 instr.addOperand(MCOperand::CreateReg(RA)); 579 if (RA == UNSUPPORTED) 582 instr.addOperand(MCOperand::CreateReg(RA)); 595 if (RD == UNSUPPORTED || RA [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 43 const MCReadAdvanceEntry *RA, 54 ReadAdvanceTable = RA; 37 InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP, unsigned NF, unsigned NP) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
H A D | Mips16FrameLowering.cpp | 73 // Registers RA, S0,S1 are the callee saved registers and they 79 // RA and return address is taken, because it has already been added in 81 // It's killed at the spill, unless the register is RA and return address 84 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA) 98 // Registers RA,S0,S1 are the callee saved registers and they will be restored 116 MF.getRegInfo().setPhysRegUsed(Mips::RA);
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H A D | MipsRegisterInfo.cpp | 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 129 // Reserve RA if in mips16 mode. 131 Reserved.set(Mips::RA);
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H A D | MipsLongBranch.cpp | 284 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 295 .addReg(Mips::RA).addReg(Mips::AT); 296 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
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/macosx-10.9.5/sudo-72/src/ |
H A D | sudoers2ldif | 20 my %RA; 59 $RA{$p2}=$p3; 92 print "sudoRunAsUser: $_\n" foreach expand(\%RA, split(/,\s*/, $runas[0])); 95 print "sudoRunAsGroup: $_\n" foreach expand(\%RA, split(/,\s*/, $runas[1]));
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/IPO/ |
H A D | DeadArgumentElimination.cpp | 145 void MarkValue(const RetOrArg &RA, Liveness L, 147 void MarkLive(const RetOrArg &RA); 149 void PropagateLiveness(const RetOrArg &RA); 571 /// MarkValue - This function marks the liveness of RA depending on L. If L is 573 /// such that RA will be marked live if any use in MaybeLiveUses gets marked 575 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument 578 case Live: MarkLive(RA); break; 585 Uses.insert(std::make_pair(*UI, RA)); 610 void DAE::MarkLive(const RetOrArg &RA) { argument 611 if (LiveFunctions.count(RA 623 PropagateLiveness(const RetOrArg &RA) argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/utils/TableGen/ |
H A D | FixedLenDecoderEmitter.cpp | 468 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex, 1391 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, 1393 if (RA == ATTR_MIXED && AllowMixed) 1395 else if (RA == ATTR_ALL_SET && !AllowMixed) 1513 bitAttr_t RA = ATTR_NONE; 1521 switch (RA) { 1528 RA = ATTR_ALL_SET; 1534 RA = ATTR_MIXED; 1543 reportRegion(RA, StartBit, BitIndex, AllowMixed); 1544 RA [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 47 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local 50 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/ |
H A D | MCSubtargetInfo.h | 55 const MCReadAdvanceEntry *RA,
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H A D | MCRegisterInfo.h | 230 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument 241 RAReg = RA;
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Analysis/ |
H A D | ScalarEvolution.cpp | 503 const Argument *RA = cast<Argument>(RV); local 504 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo(); 538 const APInt &RA = RC->getValue()->getValue(); local 539 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth(); 542 return LA.ult(RA) ? -1 : 1; 547 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local 550 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop(); 559 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands(); 565 long X = compare(LA->getOperand(i), RA->getOperand(i)); 3842 const SCEV *RA [all...] |
/macosx-10.9.5/libunwind-35.3/testsuite/ |
H A D | unwind_test_x86.s | 58 .byte 0x8 # CIE RA Column
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H A D | unwind_test_x86_64.s | 74 .byte 0x10 # CIE RA Column
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/macosx-10.9.5/cctools-845/as/ |
H A D | ppc.c | 121 #define RA(x) (((x) >> 16) & 0x1f) macro 779 * if RA == 0 or RA == RT the instruction form is invalid. 792 if(RA(insn.opcode) == 0) 793 as_bad("Invalid form of the instruction (RA must not be 0)"); 794 if(RA(insn.opcode) == RT(insn.opcode)) 795 as_bad("Invalid form of the instruction (RA must not the same " 802 * if RA == 0 the instruction form is invalid. 822 if(RA(insn.opcode) == 0) 823 as_bad("Invalid form of the instruction (RA mus [all...] |
/macosx-10.9.5/OpenLDAP-491.1/OpenLDAP/libraries/liblunicode/ucdata/ |
H A D | MUTTUCData.txt | 255 E930;DEVANAGARI HALF LETTER RA;Lo;0;L;;;;;N;;;;; 301 E97D;DEVANAGARI SIGN EYELASH RA;Lo;0;L;;;;;N;;;;; 303 E97F;DEVANAGARI SIGN SUBJOINED RA;Mn;36;L;;;;;N;;;;;
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/macosx-10.9.5/RubyCocoa-80/RubyCocoa/misc/libffi/src/powerpc/ |
H A D | darwin.S | 198 .byte 0x41 ; CIE RA Column
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H A D | darwin_closure.S | 260 .byte 0x41 ; CIE RA Column
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/macosx-10.9.5/libffi-18.1/powerpc/ |
H A D | ppc-darwin_closure.S | 249 .byte 0x41 ; CIE RA Column
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsBaseInfo.h | 205 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
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H A D | MipsMCTargetDesc.cpp | 77 InitMipsMCRegisterInfo(X, Mips::RA);
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