Searched refs:QuadDRegs (Results 1 - 1 of 1) sorted by relevance
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1497 /// QuadDRegs - Form 4 consecutive D registers.
1499 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1, function in class:ARMDAGToDAGISel
1795 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1962 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2098 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
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