/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | Thumb2RegisterInfo.h | 37 unsigned PredReg = 0,
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H A D | Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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H A D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, 35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, 109 unsigned PredReg, 115 ARMCC::CondCodes Pred, unsigned PredReg, 286 unsigned PredReg, unsigned Scratch, DebugLoc dl, 340 .addImm(Pred).addReg(PredReg).addReg(0); 351 .addImm(Pred).addReg(PredReg); 371 ARMCC::CondCodes Pred, unsigned PredReg, 416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) 448 ARMCC::CondCodes Pred, unsigned PredReg, 499 Base, false, Opcode, Pred, PredReg, Scratc 282 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument 365 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument 446 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument 529 isMatchingDecrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument 562 isMatchingIncrement(MachineInstr *MI, unsigned Base, unsigned Bytes, unsigned Limit, ARMCC::CondCodes Pred, unsigned PredReg) argument 718 unsigned PredReg = 0; local 871 unsigned PredReg = 0; local 1072 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1129 unsigned PredReg = 0; local 1249 unsigned PredReg = 0; local 1560 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument 1725 unsigned BaseReg = 0, PredReg = 0; local 1822 unsigned PredReg = 0; local [all...] |
H A D | Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; local 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); 108 unsigned PredReg = 0; local 109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 180 ARMCC::CondCodes Pred, unsigned PredReg, 195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 403 unsigned PredReg; 177 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
H A D | Thumb1RegisterInfo.h | 43 unsigned PredReg = 0,
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H A D | ARMBaseInstrInfo.h | 364 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 385 ARMCC::CondCodes Pred, unsigned PredReg, 391 ARMCC::CondCodes Pred, unsigned PredReg,
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H A D | ARMBaseRegisterInfo.cpp | 710 unsigned PredReg, unsigned MIFlags) const { 720 .addImm(0).addImm(Pred).addReg(PredReg) 749 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 752 Pred, PredReg, TII); 755 Pred, PredReg, TII); 788 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 789 unsigned PredReg = Old->getOperand(2).getReg(); local 790 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 792 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 793 unsigned PredReg local 705 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument 1129 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); local [all...] |
H A D | Thumb2ITBlockPass.cpp | 169 unsigned PredReg = 0; local 170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
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H A D | MLxExpansionPass.cpp | 284 unsigned PredReg = MI->getOperand(++NextOp).getReg(); local 297 MIB.addImm(Pred).addReg(PredReg); 309 MIB.addImm(Pred).addReg(PredReg);
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H A D | ARMBaseRegisterInfo.h | 169 unsigned PredReg = 0,
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H A D | Thumb2SizeReduction.cpp | 544 unsigned PredReg = 0; local 545 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 643 unsigned PredReg = 0; local 644 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 735 unsigned PredReg = 0; local 736 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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H A D | Thumb1RegisterInfo.cpp | 70 ARMCC::CondCodes Pred, unsigned PredReg, 80 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) 413 unsigned PredReg; 414 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { 65 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMExpandPseudoInsts.cpp | 615 unsigned PredReg = 0; local 616 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); 639 LO16.addImm(Pred).addReg(PredReg).addReg(0); 640 HI16.addImm(Pred).addReg(PredReg).addReg(0); 676 LO16.addImm(Pred).addReg(PredReg); 677 HI16.addImm(Pred).addReg(PredReg);
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H A D | ARMConstantIslandPass.cpp | 1349 unsigned PredReg = 0; local 1350 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); 1795 unsigned PredReg = 0; local 1796 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); 1814 Pred = getInstrPredicate(CmpMI, PredReg);
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H A D | ARMBaseInstrInfo.cpp | 1547 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { argument 1550 PredReg = 0; 1554 PredReg = MI->getOperand(PIdx+1).getReg(); 1577 unsigned PredReg = 0; local 1578 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1580 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1750 ARMCC::CondCodes Pred, unsigned PredReg, 1769 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1747 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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H A D | ARMISelDAGToDAG.cpp | 2479 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2480 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; 2744 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2745 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2764 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2765 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2783 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); local 2784 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/ |
H A D | PPCCTRLoops.cpp | 303 unsigned PredReg = LastI->getOperand(1).getReg(); local 347 MI->getOperand(0).getReg() == PredReg) {
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