Searched refs:LIS (Results 1 - 25 of 33) sorted by relevance

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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DLiveRangeEdit.cpp40 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
62 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
95 LiveInterval &li = LIS.getInterval(MO.getReg());
124 DefIdx = LIS.getInstructionIndex(RM.OrigMI);
127 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
151 return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
157 LIS.removeInterval(Reg);
190 LIS.getInstructionIndex(DefMI),
191 LIS.getInstructionIndex(UseMI)))
211 LIS
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H A DRegAllocBase.h64 LiveIntervals *LIS; member in class:llvm::RegAllocBase
68 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
H A DLiveDebugVariables.cpp129 LiveIntervals &LIS, const TargetInstrInfo &TII);
223 /// @param LIS Live intervals analysis.
228 LiveIntervals &LIS, MachineDominatorTree &MDT,
242 LiveIntervals &LIS);
247 LiveIntervals &LIS, MachineDominatorTree &MDT,
264 LiveIntervals &LIS, const TargetInstrInfo &TRI);
284 LiveIntervals *LIS; member in class:__anon10150::LDVImpl
470 LIS->getMBBStartIdx(MBB) :
471 LIS->getInstructionIndex(llvm::prior(MBBI)).getRegSlot();
488 LiveIntervals &LIS, MachineDominatorTre
485 extendDef(SlotIndex Idx, unsigned LocNo, LiveInterval *LI, const VNInfo *VNI, SmallVectorImpl<SlotIndex> *Kills, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
547 addDefsFromCopies(LiveInterval *LI, unsigned LocNo, const SmallVectorImpl<SlotIndex> &Kills, SmallVectorImpl<std::pair<SlotIndex, unsigned> > &NewDefs, MachineRegisterInfo &MRI, LiveIntervals &LIS) argument
620 computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
924 findInsertLocation(MachineBasicBlock *MBB, SlotIndex Idx, LiveIntervals &LIS) argument
950 insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
973 emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
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H A DInlineSpiller.cpp56 LiveIntervals &LIS; member in class:__anon10146::InlineSpiller
140 LIS(pass.getAnalysis<LiveIntervals>()),
232 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
282 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
368 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
386 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
526 LiveInterval &LI = LIS.getInterval(Reg);
527 LiveInterval &OrigLI = LIS.getInterval(Original);
572 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
578 LiveInterval &SrcLI = LIS
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H A DCalcSpillWeights.cpp46 LiveIntervals &LIS = getAnalysis<LiveIntervals>(); local
48 VirtRegAuxInfo VRAI(MF, LIS, getAnalysis<MachineLoopInfo>());
53 VRAI.CalculateWeightAndHint(LIS.getInterval(Reg));
91 const LiveIntervals &LIS,
101 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
104 if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis()))
153 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
189 if (li.isZeroLength(LIS.getSlotIndexes())) {
198 if (isRematerializable(li, LIS, *MF.getTarget().getInstrInfo()))
90 isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const TargetInstrInfo &TII) argument
H A DRegAllocBase.cpp59 LIS = &lis;
74 enqueue(&LIS->getInterval(Reg));
90 LIS->removeInterval(VirtReg->reg);
135 LIS->removeInterval(SplitVirtReg->reg);
H A DRegisterCoalescer.cpp84 LiveIntervals *LIS; member in class:__anon10191::RegisterCoalescer
382 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
412 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
414 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
415 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
437 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
451 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
490 LIS->shrinkToUses(&IntA);
504 if (LIS->hasPHIKill(IntA, AValNo))
553 SlotIndex CopyIdx = LIS
1204 LiveIntervals *LIS; member in class:__anon10192::JoinVals
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H A DSplitKit.cpp47 LIS(lis),
65 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
74 LSP.first = LIS.getInstructionIndex(FirstTerm);
85 LSP.second = LIS.getInstructionIndex(I);
93 if (!LPad || !LSP.second || !LIS.isLiveInToMBB(*CurLI, LPad))
116 if (LSP == LIS.getMBBEndIdx(MBB))
118 return LIS.getInstructionFromIndex(LSP);
138 UseSlots.push_back(LIS.getInstructionIndex(&*I).getRegSlot());
155 const_cast<LiveIntervals&>(LIS)
186 MachineFunction::iterator MFI = LIS
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H A DInterferenceCache.h57 /// LIS - Used for accessing register mask interference maps.
58 LiveIntervals *LIS; member in class:llvm::InterferenceCache::Entry
96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
103 LIS = lis;
H A DLiveRegMatrix.cpp52 LIS = &getAnalysis<LiveIntervals>();
108 LIS->checkRegMaskInterference(VirtReg, RegMaskUsable);
123 if (VirtReg.overlaps(LIS->getRegUnit(*Units), CP, *LIS->getSlotIndexes()))
H A DLiveRegMatrix.h43 LiveIntervals *LIS; member in class:llvm::LiveRegMatrix
H A DVirtRegMap.cpp153 LiveIntervals *LIS; member in class:__anon10229::VirtRegRewriter
201 LIS = &getAnalysis<LiveIntervals>();
209 LIS->addKillFlags(VRM);
235 LiveInterval &LI = LIS->getInterval(VirtReg);
236 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
H A DRegisterPressure.cpp180 LIS = lis;
221 LIS->getInstructionIndex(CurrPos).getRegSlot();
240 static_cast<IntervalPressure&>(P).BottomIdx = LIS->getMBBEndIdx(MBB);
243 LIS->getInstructionIndex(CurrPos).getRegSlot();
446 SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
492 const LiveInterval *LI = &LIS->getInterval(Reg);
515 SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
543 const LiveInterval *LI = &LIS->getInterval(Reg);
733 const LiveIntervals *LIS) {
738 SlotIndex InstSlot = LIS
730 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument
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H A DInterferenceCache.cpp90 RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
163 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
164 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
H A DLiveIntervalAnalysis.cpp1008 LiveIntervals& LIS; member in class:LiveIntervals::HMEditor
1026 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, argument
1028 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
1074 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1075 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1178 if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
1182 collectRanges(MO, &LIS.getInterval(Reg),
1240 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1243 MachineInstr* NewKillMI = LIS
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H A DRegAllocBasic.cpp205 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM);
264 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM);
H A DSplitKit.h45 const LiveIntervals &LIS; member in class:llvm::SplitAnalysis
212 LiveIntervals &LIS; member in class:llvm::SplitEditor
H A DRegAllocGreedy.cpp356 Matrix->unassign(LIS->getInterval(VirtReg));
369 LiveInterval &LI = LIS->getInterval(VirtReg);
427 LiveInterval *LI = &LIS->getInterval(~Queue.top().second);
1191 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1239 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1294 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1394 const LiveInterval &LI = LIS->getRegUnit(*Units);
1449 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
1604 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1650 if (LIS
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H A DRegAllocPBQP.cpp195 LiveIntervals *LIS = const_cast<LiveIntervals*>(lis); local
216 LiveInterval *vregLI = &LIS->getInterval(vreg);
220 LIS->checkRegMaskInterference(*vregLI, regMaskOverlaps);
238 if (vregLI->overlaps(LIS->getRegUnit(*Units))) {
H A DScheduleDAGInstrs.cpp49 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
51 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
386 assert(LIS && "vreg dependencies requires LiveIntervals");
387 LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI));
392 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DCalcSpillWeights.h44 LiveIntervals &LIS; member in class:llvm::VirtRegAuxInfo
50 MF(mf), LIS(lis), Loops(loops) {}
H A DRegisterPressure.h140 const LiveIntervals *LIS; member in class:llvm::RegPressureTracker
149 /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
165 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {}
168 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {}
H A DLiveRangeEdit.h61 LiveIntervals &LIS; member in class:llvm::LiveRangeEdit
109 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
189 /// to erase it from LIS.
H A DScheduleDAGInstrs.h116 LiveIntervals *LIS; member in class:llvm::ScheduleDAGInstrs
185 LiveIntervals *LIS = 0);
H A DMachineScheduler.h55 LiveIntervals *LIS; member in struct:llvm::MachineSchedContext
233 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),

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