Searched refs:Cond (Results 1 - 25 of 104) sorted by relevance

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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/
H A DMBlazeInstrInfo.cpp118 SmallVectorImpl<MachineOperand> &Cond,
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
147 Cond.push_back(LastInst->getOperand(0));
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
166 Cond.push_back(SecondLastInst->getOperand(0));
189 const SmallVectorImpl<MachineOperand> &Cond,
193 assert((Cond.size() == 2 || Cond.size() == 0) &&
197 if (!Cond.empty())
198 Opc = (unsigned)Cond[
115 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
187 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
H A DMBlazeInstrInfo.h200 SmallVectorImpl<MachineOperand> &Cond,
204 const SmallVectorImpl<MachineOperand> &Cond,
208 virtual bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsInstrInfo.cpp79 SmallVectorImpl<MachineOperand> &Cond) const {
86 Cond.push_back(MachineOperand::CreateImm(Opc));
89 Cond.push_back(Inst->getOperand(i));
95 SmallVectorImpl<MachineOperand> &Cond,
141 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
167 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
175 const SmallVectorImpl<MachineOperand>& Cond)
177 unsigned Opc = Cond[0].getImm();
181 for (unsigned i = 1; i < Cond.size(); ++i) {
182 if (Cond[
92 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
193 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
H A DMipsInstrInfo.h41 SmallVectorImpl<MachineOperand> &Cond,
48 const SmallVectorImpl<MachineOperand> &Cond,
52 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
85 SmallVectorImpl<MachineOperand> &Cond) const;
88 const SmallVectorImpl<MachineOperand>& Cond) const;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/
H A DXCoreInstrInfo.cpp189 SmallVectorImpl<MachineOperand> &Cond,
222 Cond.push_back(MachineOperand::CreateImm(BranchCode));
223 Cond.push_back(LastInst->getOperand(0));
244 Cond.push_back(MachineOperand::CreateImm(BranchCode));
245 Cond.push_back(SecondLastInst->getOperand(0));
277 const SmallVectorImpl<MachineOperand> &Cond,
281 assert((Cond.size() == 2 || Cond.size() == 0) &&
285 if (Cond.empty()) {
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[
187 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
275 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
H A DXCoreInstrInfo.h54 SmallVectorImpl<MachineOperand> &Cond,
59 const SmallVectorImpl<MachineOperand> &Cond,
88 SmallVectorImpl<MachineOperand> &Cond) const;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUInstrInfo.h68 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
72 SmallVectorImpl<MachineOperand> &Cond,
79 const SmallVectorImpl<MachineOperand> &Cond,
H A DSPUInstrInfo.cpp211 SmallVectorImpl<MachineOperand> &Cond,
242 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
243 Cond.push_back(LastInst->getOperand(0));
263 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
264 Cond.push_back(SecondLastInst->getOperand(0));
349 const SmallVectorImpl<MachineOperand> &Cond,
353 assert((Cond.size() == 2 || Cond.size() == 0) &&
368 if (Cond.empty()) {
384 MIB = BuildMI(&MBB, DL, get(Cond[
209 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
347 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430InstrInfo.h74 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
78 SmallVectorImpl<MachineOperand> &Cond,
84 const SmallVectorImpl<MachineOperand> &Cond,
H A DMSP430InstrInfo.cpp127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
128 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
154 Cond[0].setImm(CC);
172 SmallVectorImpl<MachineOperand> &Cond,
207 Cond.clear();
231 if (Cond.empty()) {
234 Cond.push_back(MachineOperand::CreateImm(BranchCode));
240 assert(Cond.size() == 1);
248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[
169 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
260 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
H A DMSP430BranchSelector.cpp150 SmallVector<MachineOperand, 1> Cond; local
151 Cond.push_back(I->getOperand(1));
154 TII->ReverseBranchCondition(Cond);
156 .addImm(4).addOperand(Cond[0]);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp215 SmallVectorImpl<MachineOperand> &Cond,
247 Cond.push_back(LastInst->getOperand(0));
248 Cond.push_back(LastInst->getOperand(1));
257 Cond.push_back(MachineOperand::CreateImm(1));
258 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
268 Cond.push_back(MachineOperand::CreateImm(0));
269 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
293 Cond.push_back(SecondLastInst->getOperand(0));
294 Cond.push_back(SecondLastInst->getOperand(1));
306 Cond
213 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
376 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
H A DPPCInstrInfo.h114 SmallVectorImpl<MachineOperand> &Cond,
119 const SmallVectorImpl<MachineOperand> &Cond,
145 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/
H A DNVPTXInstrInfo.h68 SmallVectorImpl<MachineOperand> &Cond,
73 const SmallVectorImpl<MachineOperand> &Cond,
H A DNVPTXInstrInfo.cpp222 SmallVectorImpl<MachineOperand> &Cond,
240 Cond.push_back(LastInst->getOperand(0));
259 Cond.push_back(SecondLastInst->getOperand(0));
304 const SmallVectorImpl<MachineOperand> &Cond,
308 assert((Cond.size() == 1 || Cond.size() == 0) &&
313 if (Cond.empty()) // Unconditional branch
317 .addReg(Cond[0].getReg()).addMBB(TBB);
323 .addReg(Cond[0].getReg()).addMBB(TBB);
219 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
302 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/
H A DSparcInstrInfo.h75 SmallVectorImpl<MachineOperand> &Cond,
82 const SmallVectorImpl<MachineOperand> &Cond,
H A DSparcInstrInfo.cpp130 SmallVectorImpl<MachineOperand> &Cond,
162 Cond.clear();
183 if (Cond.empty()) {
219 Cond.push_back(MachineOperand::CreateImm(BranchCode));
232 const SmallVectorImpl<MachineOperand> &Cond,
235 assert((Cond.size() == 1 || Cond.size() == 0) &&
238 if (Cond.empty()) {
245 unsigned CC = Cond[0].getImm();
127 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
230 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1911 ISD::CondCode Cond, bool foldBooleans,
1916 switch (Cond) {
1927 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1940 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1942 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1945 Cond = ISD::SETNE;
1949 Cond = ISD::SETEQ;
1953 Zero, Cond);
1970 if ((Cond
1910 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, DebugLoc dl) const argument
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DISDOpcodes.h770 inline bool isTrueWhenEqual(CondCode Cond) { argument
771 return ((int)Cond & 1) != 0;
778 inline unsigned getUnorderedFlavor(CondCode Cond) { argument
779 return ((int)Cond >> 3) & 3;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonInstrInfo.h59 SmallVectorImpl<MachineOperand> &Cond,
66 const SmallVectorImpl<MachineOperand> &Cond,
113 const SmallVectorImpl<MachineOperand> &Cond) const;
133 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DCodePlacementOpt.cpp78 SmallVector<MachineOperand, 4> Cond; local
79 if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond))
85 if (Cond.empty() && TBB)
107 SmallVector<MachineOperand, 4> Cond; local
109 if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond))
117 if (1u + !Cond.empty() != MBB->succ_size())
120 if (!Cond.empty() && TII->ReverseBranchCondition(Cond))
H A DMachineBasicBlock.cpp352 SmallVector<MachineOperand, 4> Cond; local
354 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
357 if (Cond.empty()) {
382 TII->InsertBranch(*this, TBB, 0, Cond, dl);
390 if (TII->ReverseBranchCondition(Cond))
393 TII->InsertBranch(*this, FBB, 0, Cond, dl);
396 TII->InsertBranch(*this, TBB, 0, Cond, dl);
420 TII->InsertBranch(*this, TBB, 0, Cond, dl);
426 if (TII->ReverseBranchCondition(Cond)) {
428 Cond
601 SmallVector<MachineOperand, 4> Cond; local
644 SmallVector<MachineOperand, 4> Cond; local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp187 Value *Cond = SI->getCondition(); local
192 if (isa<Instruction>(Cond) && cast<Instruction>(Cond)->getParent() == BB)
212 Cond, Case, *PI, BB);
241 Cond = SI->getCondition();
/macosx-10.9.5/llvmCore-3425.0.33/lib/VMCore/
H A DConstantFold.h35 Constant *ConstantFoldSelectInstruction(Constant *Cond,
/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/Utils/
H A DCloneFunction.cpp303 ConstantInt *Cond = dyn_cast<ConstantInt>(BI->getCondition()); local
305 if (Cond == 0) {
307 Cond = dyn_cast_or_null<ConstantInt>(V);
311 if (Cond) {
312 BasicBlock *Dest = BI->getSuccessor(!Cond->getZExtValue());
320 ConstantInt *Cond = dyn_cast<ConstantInt>(SI->getCondition()); local
321 if (Cond == 0) { // Or known constant after constant prop in the callee...
323 Cond = dyn_cast_or_null<ConstantInt>(V);
325 if (Cond) { // Constant fold to uncond branch!
326 SwitchInst::ConstCaseIt Case = SI->findCaseValue(Cond);
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