Searched refs:v1 (Results 1 - 16 of 16) sorted by relevance

/macosx-10.5.8/xnu-1228.15.4/osfmk/ppc/
H A DAltiAssist.s78 stvxl v1,r11,r2 ; Save V1
80 vspltisw v1,8 ; Get half of the shift
81 vslw v0,v0,v1 ; Shift half way
82 vslw v0,v0,v1 ; Shift the rest of the way (we now have 0x00010000)
83 mfvscr v1 ; Get the VSCR
84 vor v1,v1,v0 ; Turn off Java mode
86 mtvscr v1 ; Set Java mode off
87 lvxl v1,r11,r2 ; Restore V1
H A Dmovc.s242 stvx v1,r5,r9
261 lvx v1,r5,r3 // offset 16
267 stvx v1,r5,r4 // offset 16
290 lvx v1,r5,r9
313 stvx v1,r5,r9
338 lvx v1,r5,r3 // offset 16
348 stvx v1,r5,r4 // offset 16
375 lvx v1,r5,r9
H A Ddb_low_trace.c377 unsigned int v0, v1, st0, st1; local
401 v1 = (pmap->pmapCCtl >> (30 - i) & 1); /* Get high order bit */
407 v1, st1, pmap->pmapSegCache[i+1].sgcESID, pmap->pmapSegCache[i+1].sgcVSID);
H A Dstart.s388 vspltish v1,1 ; Turn on the non-Java bit and saturate
390 vxor v1,v1,v0 ; Turn off saturate and leave non-Java set
392 mtvscr v1 ; Clear the vector status register
394 vor v1,v0,v0 ; Copy into the next register
H A Dcswtch.s1624 vor v1,v31,v31 ; Copy into the next register
1724 vspltish v1,1 ; Turn on the non-Java bit and saturate
1726 vxor v1,v1,v0 ; Turn off saturate
1728 mtvscr v1 ; Set the non-java, no saturate status
1993 stvxl v1,r4,r11
2054 stvxl v1,r4,r11
2238 vor v1,v31,v31
2248 lvxl v1,r4,r11
2332 vor v1,v3
[all...]
H A Dlowmem_vectors.s1932 stvxl v1,r14,r2 ; Save a second register
1935 vspltish v1,1 ; Turn on the non-Java bit and saturate
1938 vxor v1,v1,v0 ; Turn off saturate
1939 mtvscr v1 ; Set the non-java, no saturate status for new level
1943 lvxl v1,r14,r2 ; Restore second work register
H A DFirmware.s2101 stvxl v1,0,r5
/macosx-10.5.8/xnu-1228.15.4/osfmk/ppc/commpage/
H A Dbcopy_970.s48 * v1-v8 = qw's loaded from source
309 lvx v1,0,rs // prefetch 1st source quadword
319 vperm vx,v1,v2,vp
321 vor v1,v3,v3 // v1 <- v3
379 lvx v1,0,rs // prefetch 1st source quadword
393 vperm vw,v1,v2,vp
399 lvx v1,0,rs
412 vperm vz,v8,v1,vp
422 vperm vx,v1,v
[all...]
H A Dbcopy_g4.s54 * v1-v4 = qw's loaded from source
361 lvx v1,0,rs
367 stvx v1,0,rd
378 lvx v1,0,rs
380 stvx v1,0,rd
393 lvx v1,0,rs // prefetch 1st source quadword
404 vperm vw,v1,v2,vp
405 lvx v1,0,rs
411 vperm vw,v4,v1,vp
423 vperm vx,v1,v
[all...]
H A Dbigcopy_970.s168 lvxl v1,0,rs // prime the loop
199 vperm v17,v1,v2,v0
207 lvxl v1,0,rs // peek ahead at first source quad in next chunk
237 vperm v18,v16,v1,v0
264 lvxl v1,0,rs
286 stvxl v1,0,rd
/macosx-10.5.8/xnu-1228.15.4/bsd/crypto/aes/ppc/
H A Daestab.h138 d_4(aes_32t, t_dec(i,n), isb_data, v0, v1, v2, v3);
168 d_4(aes_32t, t_dec(i,m), mm_data, v0, v1, v2, v3);
H A Daestab.c164 #define v1(p) bytes2word(fb(p), fe(p), f9(p), fd(p)) macro
232 { aes_08t p1 = x, p2 = BPOLY, n1 = hibit(x), n2 = 0x80, v1 = 1, v2 = 0; local
238 if(!n1) return v1;
242 n2 /= n1; p2 ^= p1 * n2; v2 ^= v1 * n2; n2 = hibit(p2);
249 n1 /= n2; p1 ^= p2 * n1; v1 ^= v2 * n1; n1 = hibit(p1);
/macosx-10.5.8/xnu-1228.15.4/bsd/net/
H A Ddlil.c117 } v1; member in union:if_proto::__anon176
989 error = (*ifproto->kpi.v1.input)(ifproto->ifp,
1153 ? proto->kpi.v1.event : proto->kpi.v2.event;
1283 ? proto->kpi.v1.pre_output : proto->kpi.v2.pre_output;
1462 ? proto->kpi.v1.pre_output : proto->kpi.v2.pre_output;
1645 ? proto->kpi.v1.ioctl : proto->kpi.v2.ioctl;
1739 ? proto->kpi.v1.resolve_multi : proto->kpi.v2.resolve_multi;
1780 ? proto->kpi.v1.send_arp : proto->kpi.v2.send_arp;
2106 ifproto->kpi.v1.input = proto_details->input;
2107 ifproto->kpi.v1
[all...]
/macosx-10.5.8/xnu-1228.15.4/security/
H A Dmac_vfs.c570 struct vnode *v1, struct vnode *v2)
580 MAC_CHECK(vnode_check_exchangedata, cred, v1, v1->v_label,
569 mac_vnode_check_exchangedata(vfs_context_t ctx, struct vnode *v1, struct vnode *v2) argument
H A Dmac_framework.h439 int mac_vnode_check_exchangedata(vfs_context_t ctx, struct vnode *v1,
H A Dmac_policy.h4693 @param v1 vnode 1 to swap
4694 @param vl1 Policy label for v1
4707 struct vnode *v1,

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