Searched refs:rn (Results 1 - 25 of 88) sorted by relevance

1234

/macosx-10.10.1/JavaScriptCore-7600.1.17/assembler/
H A DARM64Assembler.h902 ALWAYS_INLINE void adc(RegisterID rd, RegisterID rn, RegisterID rm)
905 insn(addSubtractWithCarry(DATASIZE, AddOp_ADD, setFlags, rm, rn, rd));
909 ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, UInt12 imm12, int shift = 0)
913 insn(addSubtractImmediate(DATASIZE, AddOp_ADD, setFlags, shift == 12, imm12, rn, rd));
917 ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm)
919 add<datasize, setFlags>(rd, rn, rm, LSL, 0);
923 ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm, ExtendType extend, int amount)
926 insn(addSubtractExtendedRegister(DATASIZE, AddOp_ADD, setFlags, rm, extend, amount, rn, rd));
930 ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftType shift, int amount)
933 if (isSp(rd) || isSp(rn)) {
[all...]
H A DARMv7Assembler.h845 void adc(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
848 ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
850 ASSERT(rn != ARMRegisters::pc);
853 m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADC_imm, rn, rd, imm);
856 void add(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
859 ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
861 ASSERT(rn != ARMRegisters::pc);
864 if (rn == ARMRegisters::sp && imm.isUInt16()) {
873 } else if (!((rd | rn) & 8)) {
875 m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_imm_T1, (RegisterID)imm.getUInt3(), rn, r
891 add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
901 add(RegisterID rd, RegisterID rn, RegisterID rm) argument
919 add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
941 add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
951 add_S(RegisterID rd, RegisterID rn, RegisterID rm) argument
959 ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
967 ARM_and(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
975 ARM_and(RegisterID rd, RegisterID rn, RegisterID rm) argument
993 asr(RegisterID rd, RegisterID rn, RegisterID rm) argument
1035 cmn(RegisterID rn, ARMThumbImmediate imm) argument
1043 cmp(RegisterID rn, ARMThumbImmediate imm) argument
1054 cmp(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1061 cmp(RegisterID rn, RegisterID rm) argument
1070 eor(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1079 eor(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1088 eor(RegisterID rd, RegisterID rn, RegisterID rm) argument
1119 ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1132 ldrWide8BitImmediate(RegisterID rt, RegisterID rn, uint8_t immediate) argument
1138 ldrCompact(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1157 ldr(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1180 ldr(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1193 ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1215 ldrh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1237 ldrh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1250 ldrb(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1261 ldrb(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1284 ldrb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1296 ldrsb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1308 ldrsh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1328 lsl(RegisterID rd, RegisterID rn, RegisterID rm) argument
1344 lsr(RegisterID rd, RegisterID rn, RegisterID rm) argument
1442 orr(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1450 orr(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1458 orr(RegisterID rd, RegisterID rn, RegisterID rm) argument
1468 orr_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1476 orr_S(RegisterID rd, RegisterID rn, RegisterID rm) argument
1494 ror(RegisterID rd, RegisterID rn, RegisterID rm) argument
1542 sdiv(RegisterID rd, RegisterID rn, RegisterID rm) argument
1552 smull(RegisterID rdLo, RegisterID rdHi, RegisterID rn, RegisterID rm) argument
1563 str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1588 str(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1611 str(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1624 strb(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1647 strb(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1670 strb(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1683 strh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1706 strh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback) argument
1729 strh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift = 0) argument
1741 sub(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1771 sub(RegisterID rd, ARMThumbImmediate imm, RegisterID rn) argument
1784 sub(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1794 sub(RegisterID rd, RegisterID rn, RegisterID rm) argument
1803 sub_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1828 sub_S(RegisterID rd, ARMThumbImmediate imm, RegisterID rn) argument
1839 sub_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1849 sub_S(RegisterID rd, RegisterID rn, RegisterID rm) argument
1857 tst(RegisterID rn, ARMThumbImmediate imm) argument
1865 tst(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift) argument
1872 tst(RegisterID rn, RegisterID rm) argument
1880 ubfx(RegisterID rd, RegisterID rn, unsigned lsb, unsigned width) argument
1889 udiv(RegisterID rd, RegisterID rn, RegisterID rm) argument
1898 vadd(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm) argument
1931 vdiv(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm) argument
1936 vldr(FPDoubleRegisterID rd, RegisterID rn, int32_t imm) argument
1941 flds(FPSingleRegisterID rd, RegisterID rn, int32_t imm) argument
1946 vmov(RegisterID rd, FPSingleRegisterID rn) argument
1952 vmov(FPSingleRegisterID rd, RegisterID rn) argument
1958 vmov(RegisterID rd1, RegisterID rd2, FPDoubleRegisterID rn) argument
1972 vmov(FPDoubleRegisterID rd, FPDoubleRegisterID rn) argument
1983 vmul(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm) argument
1988 vstr(FPDoubleRegisterID rd, RegisterID rn, int32_t imm) argument
1993 fsts(FPSingleRegisterID rd, RegisterID rn, int32_t imm) argument
1998 vsub(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm) argument
2875 vfpMemOp(OpcodeID1 op1, OpcodeID2 op2, bool size, RegisterID rn, VFPOperand rd, int32_t imm) argument
[all...]
H A DARMAssembler.h304 void emitInstruction(ARMWord op, int rd, int rn, ARMWord op2) argument
307 m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
326 void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL) argument
328 emitInstruction(toARMWord(cc) | AND, rd, rn, op2);
331 void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL) argument
333 emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2); local
336 void eor(int rd, int rn, ARMWord op2, Condition cc = AL) argument
338 emitInstruction(toARMWord(cc) | EOR, rd, rn, op2);
341 void eors(int rd, int rn, ARMWord op2, Condition cc = AL) argument
343 emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op local
346 sub(int rd, int rn, ARMWord op2, Condition cc = AL) argument
351 subs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
353 emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2); local
356 rsb(int rd, int rn, ARMWord op2, Condition cc = AL) argument
361 rsbs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
363 emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2); local
366 add(int rd, int rn, ARMWord op2, Condition cc = AL) argument
371 adds(int rd, int rn, ARMWord op2, Condition cc = AL) argument
373 emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2); local
376 adc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
381 adcs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
383 emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2); local
386 sbc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
391 sbcs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
393 emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2); local
396 rsc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
401 rscs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
403 emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2); local
406 tst(int rn, ARMWord op2, Condition cc = AL) argument
408 emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2); local
411 teq(int rn, ARMWord op2, Condition cc = AL) argument
413 emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2); local
416 cmp(int rn, ARMWord op2, Condition cc = AL) argument
418 emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2); local
421 cmn(int rn, ARMWord op2, Condition cc = AL) argument
423 emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2); local
426 orr(int rd, int rn, ARMWord op2, Condition cc = AL) argument
431 orrs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
433 emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2); local
460 bic(int rd, int rn, ARMWord op2, Condition cc = AL) argument
465 bics(int rd, int rn, ARMWord op2, Condition cc = AL) argument
467 emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2); local
480 mul(int rd, int rn, int rm, Condition cc = AL) argument
485 muls(int rd, int rn, int rm, Condition cc = AL) argument
490 mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL) argument
575 halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) argument
577 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm); local
585 halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) argument
828 vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn) argument
1008 revertBranchPtrWithPatch(void* instructionStart, RegisterID rn, ARMWord imm) argument
[all...]
H A DMacroAssemblerARM64.h2579 ALWAYS_INLINE void loadUnsignedImmediate(RegisterID rt, RegisterID rn, unsigned pimm)
2581 m_assembler.ldr<datasize>(rt, rn, pimm);
2585 ALWAYS_INLINE void loadUnscaledImmediate(RegisterID rt, RegisterID rn, int simm)
2587 m_assembler.ldur<datasize>(rt, rn, simm);
2591 ALWAYS_INLINE void storeUnsignedImmediate(RegisterID rt, RegisterID rn, unsigned pimm)
2593 m_assembler.str<datasize>(rt, rn, pimm);
2597 ALWAYS_INLINE void storeUnscaledImmediate(RegisterID rt, RegisterID rn, int simm)
2599 m_assembler.stur<datasize>(rt, rn, simm);
2764 ALWAYS_INLINE bool tryLoadWithOffset(RegisterID rt, RegisterID rn, int32_t offset) argument
2767 loadUnscaledImmediate<datasize>(rt, rn, offse
2778 tryLoadWithOffset(FPRegisterID rt, RegisterID rn, int32_t offset) argument
2792 tryStoreWithOffset(RegisterID rt, RegisterID rn, int32_t offset) argument
2806 tryStoreWithOffset(FPRegisterID rt, RegisterID rn, int32_t offset) argument
[all...]
/macosx-10.10.1/xnu-2782.1.97/bsd/net/
H A Dradix.c113 #define RN_MATCHF(rn, f, arg) (f == NULL || (*f)((rn), arg))
941 struct radix_node *rn, *last; local
965 for (rn = h->rnh_treetop; rn->rn_bit >= 0; ) {
966 last = rn;
967 if (!(rn->rn_bmask & xm[rn->rn_offset]))
970 if (rn->rn_bmask & xa[rn
1063 struct radix_node *rn; local
[all...]
H A Droute.c794 rn_match_ifscope(struct radix_node *rn, void *arg) argument
796 struct rtentry *rt = (struct rtentry *)rn;
1676 struct radix_node *rn; local
1752 if ((rn = rnh->rnh_deladdr(dst, netmask, rnh)) == NULL)
1754 if (rn->rn_flags & (RNF_ACTIVE | RNF_ROOT)) {
1758 rt = (struct rtentry *)rn;
2035 rn = rnh->rnh_addaddr((caddr_t)ndst, (caddr_t)netmask,
2037 if (rn == 0) {
2062 rn = rnh->rnh_addaddr((caddr_t)ndst,
2074 if (rn
2219 rt_fixdelete(struct radix_node *rn, void *vp) argument
2256 rt_fixchange(struct radix_node *rn, void *vp) argument
2690 struct radix_node *rn; local
2764 struct radix_node *rn0, *rn; local
[all...]
/macosx-10.10.1/vim-55/src/
H A Dswis.s4 ar0 rn 0
5 ar1 rn 1
6 ar2 rn 2
7 ar3 rn 3
8 ar4 rn 4
9 ar5 rn 5
10 ar6 rn 6
11 ar7 rn 7
12 ar10 rn 10
13 ar11 rn 1
[all...]
/macosx-10.10.1/OpenSSH-189/osslshim/ossl/
H A Dossl-lhash.c212 LHASH_NODE *nn, **rn; local
220 rn = getrn(lh, data, &hash);
222 if (*rn == NULL) {
232 *rn = nn;
238 ret = (*rn)->data;
239 (*rn)->data = data;
250 LHASH_NODE *nn, **rn; local
254 rn = getrn(lh, data, &hash);
256 if (*rn == NULL) {
260 nn = *rn;
281 LHASH_NODE **rn; local
[all...]
/macosx-10.10.1/OpenSSL098-52/src/crypto/lhash/
H A Dlhash.c182 LHASH_NODE *nn,**rn; local
189 rn=getrn(lh,data,&hash);
191 if (*rn == NULL)
203 *rn=nn;
210 ret= (*rn)->data;
211 (*rn)->data=data;
220 LHASH_NODE *nn,**rn; local
224 rn=getrn(lh,data,&hash);
226 if (*rn == NULL)
233 nn= *rn;
251 LHASH_NODE **rn; local
[all...]
/macosx-10.10.1/Security-57031.1.35/Security/libsecurity_apple_csp/open_ssl/lhash/
H A Dlhash.c200 LHASH_NODE *nn,**rn; local
207 rn=getrn(lh,data,&hash);
209 if (*rn == NULL)
221 *rn=nn;
228 ret= (*rn)->data;
229 (*rn)->data=data;
238 LHASH_NODE *nn,**rn; local
242 rn=getrn(lh,data,&hash);
244 if (*rn == NULL)
251 nn= *rn;
269 LHASH_NODE **rn; local
[all...]
/macosx-10.10.1/cxxfilt-11/cxxfilt/opcodes/
H A Dsh-dis.c34 int rn,
51 fprintf_fn (stream, "@r%d", rn);
58 fprintf_fn (stream, "@r%d+", rn);
62 fprintf_fn (stream, "@r%d+r8", rn);
66 fprintf_fn (stream, "@r%d+r9", rn);
499 int rn = 0; local
637 rn = nibs[n];
645 rn = (nibs[n] & 0xc) >> 2;
648 rn = (nibs[n] & 0xc) >> 2;
656 rn
33 print_movxy(const sh_opcode_info *op, int rn, int rm, fprintf_ftype fprintf_fn, void *stream) argument
[all...]
H A Dh8500-dis.c94 int rn = 0; local
126 rn = buffer[byte] & 0x7;
220 func (stream, "@(0x%x:16,r%d)", disp, rn);
223 func (stream, "@(0x%x:8 (%d),r%d)", disp & 0xff, disp, rn);
239 func (stream, "r%d", rn);
248 func (stream, "@-r%d", rn);
251 func (stream, "@r%d+", rn);
254 func (stream, "@r%d", rn);
H A Dh8300-dis.c191 int rn,
217 outfn (stream, "%s", regnames[rn]);
221 outfn (stream, "%s", wregnames[rn]);
225 outfn (stream, "%s", lregnames[rn]);
235 outfn (stream, "%s.b", regnames[rn < 8 ? rn + 8 : rn]);
240 outfn (stream, "%s.w", wregnames[rn < 8 ? rn : rn
185 print_one_arg(disassemble_info *info, bfd_vma addr, op_type x, int cst, int cstlen, int rdisp_n, int rn, const char **pregnames, int len) argument
[all...]
/macosx-10.10.1/JavaScriptCore-7600.1.17/disassembler/ARMv7/
H A DARMv7DOpcode.cpp359 appendRegisterName(rn());
371 appendRegisterName(rn());
425 appendRegisterName(rn());
435 appendRegisterName(rn());
445 appendRegisterName(rn());
507 appendRegisterName(rn());
527 appendRegisterName(rn());
796 if (rn() == 15) {
845 appendRegisterName(rn());
857 appendRegisterName(rn());
[all...]
H A DARMv7DOpcode.h262 unsigned rn() { return (m_opcode >> 3) & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractT1
279 unsigned rn() { return (m_opcode >> 3) & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeAddSubtractImmediate3
350 unsigned rn() { return (m_opcode >> 8) & 0x3; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeCompareImmediateT1
364 unsigned rn() { return m_opcode & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT1
377 unsigned rn() { return ((m_opcode >> 4) & 0x8) | (m_opcode & 0x7); } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeCompareRegisterT2
442 unsigned rn() { return (m_opcode >> 3) & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterImmediate
480 unsigned rn() { return (m_opcode >> 3) & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeLoadStoreRegisterOffsetT1
578 unsigned rn() { return m_opcode & 0x7; } function in class:JSC::ARMv7Disassembler::ARMv7DOpcodeMiscCompareAndBranch
712 unsigned rn() { return (m_opcode >> 16) & 0xf; } function in class:JSC::ARMv7Disassembler::ARMv7D32BitOpcode
/macosx-10.10.1/JavaScriptCore-7600.1.17/disassembler/ARM64/
H A DA64DOpcode.cpp209 appendSPOrRegisterName(rn(), is64Bit());
234 appendSPOrRegisterName(rn(), is64Bit());
238 if (option() == 0x2 && ((rd() == 31) || (rn() == 31)))
269 appendRegisterName(rn(), is64Bit());
316 appendRegisterName(rn(), false);
327 appendRegisterName(rn(), is64Bit());
338 appendRegisterName(rn(), is64Bit());
349 appendRegisterName(rn(), is64Bit());
362 appendRegisterName(rn(), is64Bit());
374 appendRegisterName(rn(), is64Bi
[all...]
/macosx-10.10.1/swig-12/Source/Swig/
H A Dnaming.c418 DOH *rn = 0; local
422 rn = Getattr(n, decl);
424 rn = Getattr(n, "start");
426 return rn;
431 DOH *rn = 0; local
434 rn = get_object(n, decl);
435 if ((!rn) && ncdecl)
436 rn = get_object(n, ncdecl);
437 if (!rn)
438 rn
445 DOH *rn = 0; local
1187 Swig_name_match_nameobj(Hash *rn, Node *n) argument
1241 Hash *rn = Getitem(namelist, i); local
1483 Hash *rn = Swig_name_object_get(Swig_name_rename_hash(), prefix, name, decl); local
[all...]
/macosx-10.10.1/xnu-2782.1.97/bsd/netinet/
H A Din_rmx.c253 struct radix_node *rn; local
257 rn = rn_delete(v_arg, netmask_arg, head);
258 if (rt_verbose > 1 && rn != NULL) {
260 struct rtentry *rt = (struct rtentry *)rn;
269 return (rn);
276 in_validate(struct radix_node *rn) argument
278 struct rtentry *rt = (struct rtentry *)rn;
304 return (rn);
325 struct radix_node *rn = rn_match_args(v_arg, head, f, w); local
327 if (rn !
358 in_clsroute(struct radix_node *rn, struct radix_node_head *head) argument
458 in_rtqkill(struct radix_node *rn, void *rock) argument
707 in_ifadownkill(struct radix_node *rn, void *xap) argument
[all...]
/macosx-10.10.1/xnu-2782.1.97/bsd/netinet6/
H A Din6_rmx.c335 struct radix_node *rn; local
339 rn = rn_delete(v_arg, netmask_arg, head);
340 if (rn != NULL) {
341 struct rtentry *rt = (struct rtentry *)rn;
357 return (rn);
364 in6_validate(struct radix_node *rn) argument
366 struct rtentry *rt = (struct rtentry *)rn;
392 return (rn);
413 struct radix_node *rn = rn_match_args(v_arg, head, f, w); local
415 if (rn !
445 in6_clsroute(struct radix_node *rn, struct radix_node_head *head) argument
547 in6_rtqkill(struct radix_node *rn, void *rock) argument
[all...]
/macosx-10.10.1/tcl-105/tcl_ext/mk4tcl/metakit/examples/
H A Dmillions.py63 rn = self.recnos
64 if not rn: return 0
65 return rn[-1]+len(self.view[-1].data)
105 rn = self.recnos
106 pos = self.bisect(rn, idx)-1
107 base = rn[pos]
/macosx-10.10.1/file-46/file/src/
H A Dcompress.c148 size_t rn = n; local
162 return rn;
176 size_t rn = n; local
211 rn = n;
223 return rn - n;
230 return rn;
/macosx-10.10.1/ICU-531.30/icuSources/i18n/
H A Duspoof_wsconf.cpp319 for (int32_t rn=0; rn<ignoreSet.getRangeCount(); rn++) {
320 UChar32 rangeStart = ignoreSet.getRangeStart(rn);
321 UChar32 rangeEnd = ignoreSet.getRangeEnd(rn);
/macosx-10.10.1/emacs-93/emacs/src/
H A Dfringe.c915 int y = 0, rn;
927 for (y = 0, rn = 0, row = w->current_matrix->rows;
928 y < yb && rn < nrows;
929 y += row->height, ++row, ++rn)
954 int rn, nrows = w->current_matrix->nrows;
995 for (y = 0, rn = 0;
996 y < yb && rn < nrows;
997 y += row->height, ++rn)
1002 row = w->desired_matrix->rows + rn;
1004 row = w->current_matrix->rows + rn;
914 int y = 0, rn; local
953 int rn, nrows = w->current_matrix->nrows; local
[all...]
/macosx-10.10.1/tcl-105/tcl_ext/tcllib/tcllib/modules/struct/
H A Dmatrix1.tcl928 for {set r $row; set rn [expr {$r + 1}]} {$rn < $rows} {incr r ; incr rn} {
929 set data($c,$r) $data($c,$rn)
930 if {[info exists rowh($rn)]} {
931 set rowh($r) $rowh($rn)
932 unset rowh($rn)
1323 for {set rn $rows ; set r [expr {$rn - 1}]} {$r >= $firstrow} {incr r -1 ; incr rn
[all...]
/macosx-10.10.1/xnu-2782.1.97/tools/lldbmacros/
H A Dnet.py699 rn = Cast(rt_tables.rnh_treetop, 'radix_node *')
702 while (rn.rn_bit >= 0):
703 rn = rn.rn_u.rn_node.rn_L
706 base = Cast(rn, 'radix_node *')
707 while ((rn.rn_parent.rn_u.rn_node.rn_R == rn) and (rn.rn_flags & RNF_ROOT == 0)):
708 rn = rn
[all...]

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