Searched refs:imm3 (Results 1 - 4 of 4) sorted by relevance
| /macosx-10.10.1/dyld-353.2.1/launch-cache/ |
| H A D | MachORebaser.hpp | 597 uint32_t imm3 = ((instruction & 0x70000000) >> 28); local
599 uint32_t imm16 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
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| /macosx-10.10.1/cxxfilt-11/cxxfilt/opcodes/ |
| H A D | bfin-dis.c | 80 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0},
388 #define imm3(x) fmtconst (c_imm3, x, 0, outf) macro
890 OUTS (outf, imm3 (y));
897 OUTS (outf, imm3 (y));
904 OUTS (outf, imm3 (y));
964 OUTS (outf, imm3 (y));
971 OUTS (outf, imm3 (y));
978 OUTS (outf, imm3 (y));
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| /macosx-10.10.1/JavaScriptCore-7600.1.17/assembler/ |
| H A D | ARMv7Assembler.h | 262 unsigned imm3 : 3;
2765 return (imm.m_value.imm3 << 12) | (rd << 8) | imm.m_value.imm8;
2770 result.m_value.imm3 = (value >> 12) & 7;
2855 ALWAYS_INLINE void twoWordOp12Reg40Imm3Reg4Imm20Imm5(OpcodeID1 op, RegisterID reg1, RegisterID reg2, uint16_t imm1, uint16_t imm2, uint16_t imm3) argument
2858 m_buffer.putShort((imm1 << 12) | (reg2 << 8) | (imm2 << 6) | imm3);
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| H A D | ARM64Assembler.h | 3256 ALWAYS_INLINE static int addSubtractExtendedRegister(Datasize sf, AddOp op, SetFlags S, RegisterID rm, ExtendType option, int imm3, RegisterID rn, RegisterID rd)
3258 ASSERT(imm3 < 5);
3261 return (0x0b200000 | sf << 31 | op << 30 | S << 29 | opt << 22 | xOrZr(rm) << 16 | option << 13 | (imm3 & 0x7) << 10 | xOrSp(rn) << 5 | xOrZrOrSp(S, rd));
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