/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/ |
H A D | ARMAsmPrinter.cpp | 1051 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); 1052 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 1053 BrInst.addOperand(MCOperand::CreateReg(0)); 1103 Inst.addOperand(MCOperand::CreateReg(Dest)); 1104 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); 1106 Inst.addOperand(MCOperand::CreateImm(pred)); 1107 Inst.addOperand(MCOperand::CreateReg(ccreg)); 1328 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1329 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1331 TmpInst.addOperand(MCOperan [all...] |
H A D | ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::CreateImm(0)); 40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 41 NopInst.addOperand(MCOperand::CreateReg(0)); 44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); 45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); 46 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 47 NopInst.addOperand(MCOperand::CreateReg(0)); 48 NopInst.addOperand(MCOperand::CreateReg(0));
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H A D | Thumb1InstrInfo.cpp | 31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 34 NopInst.addOperand(MCOperand::CreateReg(0));
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H A D | ARMExpandPseudoInsts.cpp | 81 UseMI.addOperand(MO); 83 DefMI.addOperand(MO); 400 MIB.addOperand(MI.getOperand(OpIdx++)); 403 MIB.addOperand(MI.getOperand(OpIdx++)); 404 MIB.addOperand(MI.getOperand(OpIdx++)); 407 MIB.addOperand(MI.getOperand(OpIdx++)); 417 MIB.addOperand(MI.getOperand(OpIdx++)); 418 MIB.addOperand(MI.getOperand(OpIdx++)); 425 MIB.addOperand(MO); 452 MIB.addOperand(M [all...] |
H A D | Thumb2SizeReduction.cpp | 458 MIB.addOperand(MI->getOperand(0)); 459 MIB.addOperand(MI->getOperand(1)); 472 MIB.addOperand(MI->getOperand(OpNum)); 519 .addOperand(MI->getOperand(0)) 520 .addOperand(MI->getOperand(1)) 675 MIB.addOperand(MI->getOperand(0)); 690 MIB.addOperand(MI->getOperand(i)); 766 MIB.addOperand(MI->getOperand(0)); 795 MIB.addOperand(MO);
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H A D | ARMMCInstLower.cpp | 123 OutMI.addOperand(MCOp);
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H A D | Thumb2ITBlockPass.cpp | 185 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 210 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 1396 Inst.addOperand(MCOperand::CreateImm(0)); 1398 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1400 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1405 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1407 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1412 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1417 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1422 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1427 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1432 Inst.addOperand(MCOperan [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 344 Inst.addOperand(MCOperand::CreateReg(Reg)); 355 Inst.addOperand(MCOperand::CreateReg(Reg)); 374 Inst.addOperand(MCOperand::CreateReg(Reg)); 386 Inst.addOperand(MCOperand::CreateReg(Reg)); 394 Inst.addOperand(MCOperand::CreateReg(RegNo)); 410 Inst.addOperand(MCOperand::CreateReg(Reg)); 413 Inst.addOperand(MCOperand::CreateReg(Reg)); 414 Inst.addOperand(MCOperand::CreateReg(Base)); 415 Inst.addOperand(MCOperand::CreateImm(Offset)); 431 Inst.addOperand(MCOperan [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 63 MI->addOperand(MachineOperand::CreateReg(RegNo, 79 MI->addOperand(MachineOperand::CreateImm(Val)); 84 MI->addOperand(MachineOperand::CreateCImm(Val)); 89 MI->addOperand(MachineOperand::CreateFPImm(Val)); 95 MI->addOperand(MachineOperand::CreateMBB(MBB, TargetFlags)); 100 MI->addOperand(MachineOperand::CreateFI(Idx)); 107 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); 113 MI->addOperand(MachineOperand::CreateTargetIndex(Idx, Offset, TargetFlags)); 119 MI->addOperand(MachineOperand::CreateJTI(Idx, TargetFlags)); 126 MI->addOperand(MachineOperan 153 const MachineInstrBuilder &addOperand(const MachineOperand &MO) const { function in class:llvm::MachineInstrBuilder [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 548 instr.addOperand(MCOperand::CreateReg(RD)); 549 instr.addOperand(MCOperand::CreateReg(RB)); 550 instr.addOperand(MCOperand::CreateReg(RA)); 556 instr.addOperand(MCOperand::CreateReg(RD)); 557 instr.addOperand(MCOperand::CreateReg(RA)); 558 instr.addOperand(MCOperand::CreateReg(RB)); 564 instr.addOperand(MCOperand::CreateReg(RD)); 565 instr.addOperand(MCOperand::CreateReg(RA)); 575 instr.addOperand(MCOperand::CreateReg(RD)); 576 instr.addOperand(MCOperan [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 230 OutMI.addOperand(OutMI.getOperand(0)); 231 OutMI.addOperand(OutMI.getOperand(0)); 253 Inst.addOperand(Saved); 304 Inst.addOperand(Saved); 349 OutMI.addOperand(MCOp); 400 OutMI.addOperand(Saved); 426 OutMI.addOperand(Saved); 538 OutMI.addOperand(MCOperand::CreateReg(X86::R10)); 539 OutMI.addOperand(MCOperand::CreateReg(X86::RAX)); 587 LEA.addOperand(MCOperan [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 595 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 597 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 599 MI.addOperand(MCOperand::CreateExpr(Expr)); 919 Inst.addOperand(MCOperand::CreateReg(Register)); 969 Inst.addOperand(MCOperand::CreateReg(Register)); 996 Inst.addOperand(MCOperand::CreateReg(Register)); 1017 Inst.addOperand(MCOperand::CreateReg(Register)); 1051 Inst.addOperand(MCOperand::CreateReg(Register)); 1070 Inst.addOperand(MCOperand::CreateReg(Register)); 1093 Inst.addOperand(MCOperan [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 398 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 400 Inst.addOperand(MCOperand::CreateExpr(Expr)); 405 Inst.addOperand(MCOperand::CreateReg(getReg())); 449 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg())); 450 Inst.addOperand(MCOperand::CreateImm(getMemScale())); 451 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg())); 453 Inst.addOperand(MCOperand::CreateReg(getMemSegReg())); 460 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 462 Inst.addOperand(MCOperand::CreateExpr(getMemDisp())); 1524 TmpInst.addOperand(MCOperan [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 225 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 240 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 252 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 346 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 365 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 368 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 374 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, Imp)); 376 MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask())); 378 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 381 MI->addOperand(MachineOperan [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 174 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 285 MI.addOperand(MCOperand::CreateExpr(Expr)); 385 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); 388 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); 420 mcInst.addOperand(MCOperand::CreateImm(immediate)); 451 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 631 mcInst.addOperand(baseReg); 632 mcInst.addOperand(scaleAmount); 633 mcInst.addOperand(indexReg); 637 mcInst.addOperand(displacemen [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 179 Inst.addOperand(MCOperand::CreateImm(0)); 181 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 183 Inst.addOperand(MCOperand::CreateExpr(Expr)); 188 Inst.addOperand(MCOperand::CreateReg(getReg())); 204 Inst.addOperand(MCOperand::CreateReg(getMemBase())); 208 Inst.addOperand(MCOperand::CreateReg(RegOff));
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/macosx-10.10.1/llvmCore-3425.0.34/unittests/VMCore/ |
H A D | MetadataTest.cpp | 143 NMD->addOperand(n); 144 NMD->addOperand(n2);
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonMCInstLower.cpp | 91 MCI.addOperand(MCO);
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H A D | HexagonPeephole.cpp | 200 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); 207 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/ |
H A D | MSP430BranchSelector.cpp | 156 .addImm(4).addOperand(Cond[0]);
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H A D | MSP430MCInstLower.cpp | 151 OutMI.addOperand(MCOp);
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/ |
H A D | VectorElementize.cpp | 264 copy->addOperand(MachineOperand::CreateReg(scalarRegs[i], true)); 268 copy->addOperand(otherOperands[i]); 300 copy->addOperand(MachineOperand::CreateReg(scalarRegs[i], false)); 303 copy->addOperand(otherOperands[i]); 339 copy->addOperand(MachineOperand::CreateReg(src1[elem], false)); 341 copy->addOperand(MachineOperand::CreateReg(src2[elem], false)); 364 copy->addOperand(MachineOperand::CreateReg(src[which.getImm()], false)); 396 copy->addOperand(MachineOperand::CreateReg(src[i], false)); 398 copy->addOperand(Instr->getOperand(2)); 425 copy->addOperand(Inst [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/MC/ |
H A D | MCInst.h | 167 void addOperand(const MCOperand &Op) { function in class:llvm::MCInst
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/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/ |
H A D | Metadata.h | 229 /// addOperand - Add metadata operand. 230 void addOperand(MDNode *M);
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