Searched refs:SRI (Results 1 - 4 of 4) sorted by relevance
/macosx-10.10.1/llvmCore-3425.0.34/lib/MC/ |
H A D | MCRegisterInfo.cpp | 31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; 32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) 33 if (*SRI == Idx) 42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; 43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) 45 return *SRI;
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 214 MCSuperRegIterator SRI(Reg, TRI); 215 assert(SRI.isValid() && "Expected a superreg"); 216 unsigned SuperReg = *SRI; 217 ++SRI; 218 assert(!SRI.isValid() && "Expected exactly one superreg");
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/macosx-10.10.1/llvmCore-3425.0.34/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 265 SubRegMap::const_iterator SRI = Map.find(I->first); local 266 if (SRI == Map.end()) 268 // Add I->second as a name for the subreg SRI->second, assuming it is 270 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) 273 SubRegs.insert(std::make_pair(I->second, SRI->second)); 1365 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(), 1366 SRE = SRM.end(); SRI != SRE; ++SRI) { 1367 if (SRI->second == Reg) 1370 Changed |= normalizeWeight(SRI [all...] |
H A D | CodeGenSchedule.cpp | 286 for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) { 287 assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite"); 288 SchedReads.push_back(CodeGenSchedRW(SchedReads.size(), *SRI));
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