Searched refs:Opcode (Results 1 - 25 of 151) sorted by relevance

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/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/MC/
H A DMCInstrInfo.h48 const MCInstrDesc &get(unsigned Opcode) const {
49 assert(Opcode < NumOpcodes && "Invalid opcode!");
50 return Desc[Opcode];
54 const char *getName(unsigned Opcode) const {
55 assert(Opcode < NumOpcodes && "Invalid opcode!");
56 return &InstrNameData[InstrNameIndices[Opcode]];
H A DMCInst.h151 unsigned Opcode; member in class:llvm::MCInst
155 MCInst() : Opcode(0) {}
157 void setOpcode(unsigned Op) { Opcode = Op; }
158 unsigned getOpcode() const { return Opcode; }
H A DMCInstPrinter.h55 StringRef getOpcodeName(unsigned Opcode) const;
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp206 unsigned Opcode; local
211 case MVT::i8: Opcode = NVPTX::LD_i8_avar; break;
212 case MVT::i16: Opcode = NVPTX::LD_i16_avar; break;
213 case MVT::i32: Opcode = NVPTX::LD_i32_avar; break;
214 case MVT::i64: Opcode = NVPTX::LD_i64_avar; break;
215 case MVT::f32: Opcode = NVPTX::LD_f32_avar; break;
216 case MVT::f64: Opcode = NVPTX::LD_f64_avar; break;
217 case MVT::v2i8: Opcode = NVPTX::LD_v2i8_avar; break;
218 case MVT::v2i16: Opcode = NVPTX::LD_v2i16_avar; break;
219 case MVT::v2i32: Opcode
391 unsigned Opcode; local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/MC/
H A DMCInstPrinter.cpp23 StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const {
24 return MII.getName(Opcode);
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.h33 Predicate InvertPredicate(Predicate Opcode);
H A DPPCPredicates.cpp19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { argument
20 switch (Opcode) {
/macosx-10.10.1/JavaScriptCore-7600.1.17/llint/
H A DLLIntData.h30 #include "Opcode.h"
51 static Opcode s_opcodeMap[numOpcodeIDs];
56 friend Opcode* opcodeMap();
57 friend Opcode getOpcode(OpcodeID);
68 inline Opcode* opcodeMap()
73 inline Opcode getOpcode(OpcodeID id)
78 return static_cast<Opcode>(id);
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/
H A DMipsDirectObjLower.cpp58 int Opcode = InstIn.getOpcode(); local
60 if (Opcode == Mips::DEXT)
77 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
83 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp90 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, argument
94 const MCInstrDesc &MCID = TII.get(Opcode);
145 unsigned Opcode = MI->getOpcode(); local
148 GetInstrType(Opcode, isFirst, isSingle, isCracked,
182 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
203 unsigned Opcode = MI->getOpcode(); local
206 GetInstrType(Opcode, isFirst, isSingle, isCracked,
211 if (Opcode == PPC::MTCTR || Opcode
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp47 const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii) { argument
49 return MII->getName(Opcode);
351 uint32_t Opcode = mcInst.getOpcode(); local
358 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
359 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
360 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
361 Opcode !
510 uint32_t Opcode = mcInst.getOpcode(); local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { argument
24 switch (Opcode) {
H A DARMHazardRecognizer.cpp26 unsigned Opcode = MCID.getOpcode(); local
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
H A DARMLoadStoreOptimizer.cpp94 int Offset, unsigned Base, bool BaseKill, int Opcode,
107 int Opcode,
114 int Opcode, unsigned Size,
137 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) { argument
138 switch (Opcode) {
208 AMSubMode getLoadStoreMultipleSubMode(int Opcode) { argument
209 switch (Opcode) {
285 int Opcode, ARMCC::CondCodes Pred,
296 bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
282 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument
365 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument
446 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument
720 int Opcode = MI->getOpcode(); local
854 int Opcode = MI->getOpcode(); local
1012 int Opcode = MI->getOpcode(); local
1049 int Opcode = MI->getOpcode(); local
1099 unsigned Opcode = MI->getOpcode(); local
1243 int Opcode = MBBI->getOpcode(); local
1399 unsigned Opcode = PrevMI->getOpcode(); local
1573 unsigned Opcode = Op0->getOpcode(); local
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/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DFastISel.h105 bool SelectOperator(const User *I, unsigned Opcode);
165 unsigned Opcode);
173 unsigned Opcode,
182 unsigned Opcode,
192 unsigned Opcode,
202 unsigned Opcode,
212 unsigned Opcode,
222 unsigned Opcode,
231 unsigned Opcode,
239 unsigned Opcode,
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H A DSelectionDAG.h558 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT);
559 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N);
560 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2);
561 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
563 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
565 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
568 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
570 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
572 SDValue getNode(unsigned Opcode, DebugLoc DL,
575 SDValue getNode(unsigned Opcode, DebugLo
918 isCommutativeBinOp(unsigned Opcode) argument
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp231 unsigned Opcode = J->getOpcode(); local
232 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
233 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
234 bool UseSignedOp = Opcode == Instruction::SDiv ||
235 Opcode == Instruction::SRem;
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/
H A DXCoreFrameLowering.cpp54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; local
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6; local
70 BuildMI(MBB, I, dl, TII.get(Opcode))
125 int Opcode; local
127 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
132 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
134 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
262 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6; local
263 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
266 int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; local
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp80 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
82 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
302 unsigned Opcode = 0; local
319 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
320 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
321 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
322 else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed;
327 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
346 unsigned Opcode,
362 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, d
345 SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode, DebugLoc dl) argument
409 SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode, DebugLoc dl) argument
494 unsigned Opcode = 0; local
611 unsigned Opcode = 0; local
637 unsigned Opcode = 0; local
670 unsigned Opcode = 0; local
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Transforms/Scalar/
H A DReassociate.cpp160 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode) { argument
162 cast<Instruction>(V)->getOpcode() == Opcode)
270 static void IncorporateWeight(APInt &LHS, const APInt &RHS, unsigned Opcode) { argument
288 if (Instruction::isIdempotent(Opcode)) {
295 if (Instruction::isNilpotent(Opcode)) {
301 if (Opcode == Instruction::Add) {
307 assert(Opcode == Instruction::Mul && "Unknown associative operation!");
344 static Constant *EvaluateRepeatedConstant(unsigned Opcode, Constant *C, argument
348 if (Opcode == Instruction::Add)
359 Result = Result ? ConstantExpr::get(Opcode, Resul
454 unsigned Opcode = I->getOpcode(); local
671 unsigned Opcode = I->getOpcode(); local
1041 OptimizeAndOrXor(unsigned Opcode, SmallVectorImpl<ValueEntry> &Ops) argument
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/VMCore/
H A DInstruction.cpp382 bool Instruction::isAssociative(unsigned Opcode) { argument
383 return Opcode == And || Opcode == Or || Opcode == Xor ||
384 Opcode == Add || Opcode == Mul;
415 bool Instruction::isIdempotent(unsigned Opcode) { argument
416 return Opcode == And || Opcode == Or;
428 bool Instruction::isNilpotent(unsigned Opcode) { argument
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/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp267 static int isSignedOp(ISD::CondCode Opcode) { argument
268 switch (Opcode) {
1536 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1537 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op);
2418 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT) { argument
2420 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
2425 SDNode *N = new (NodeAllocator) SDNode(Opcode, DL, getVTList(VT));
2435 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, argument
2440 switch (Opcode) {
2454 Opcode
2702 FoldConstantArithmetic(unsigned Opcode, EVT VT, ConstantSDNode *Cst1, ConstantSDNode *Cst2) argument
2738 getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2) argument
3201 getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) argument
3291 getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument
3298 getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument
3937 getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
3965 getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
3995 getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value* PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
4026 getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
4068 getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, const Value* PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
4099 getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
4140 getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, const EVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol, bool ReadMem, bool WriteMem) argument
4152 getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol, bool ReadMem, bool WriteMem) argument
4175 getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, EVT MemVT, MachineMemOperand *MMO) argument
4517 getNode(unsigned Opcode, DebugLoc DL, EVT VT, const SDUse *Ops, unsigned NumOps) argument
4533 getNode(unsigned Opcode, DebugLoc DL, EVT VT, const SDValue *Ops, unsigned NumOps) argument
4588 getNode(unsigned Opcode, DebugLoc DL, const std::vector<EVT> &ResultTys, const SDValue *Ops, unsigned NumOps) argument
4595 getNode(unsigned Opcode, DebugLoc DL, const EVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps) argument
4603 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, const SDValue *Ops, unsigned NumOps) argument
4670 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) argument
4674 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1) argument
4680 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2) argument
4686 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) argument
4692 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument
4699 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument
5131 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT) argument
5137 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1) argument
5144 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument
5152 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument
5160 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, const SDValue *Ops, unsigned NumOps) argument
5167 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2) argument
5173 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1) argument
5181 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument
5189 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
5198 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, const SDValue *Ops, unsigned NumOps) argument
5206 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument
5215 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
5224 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps) argument
5232 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps) argument
5240 getMachineNode(unsigned Opcode, DebugLoc dl, const std::vector<EVT> &ResultTys, const SDValue *Ops, unsigned NumOps) argument
5248 getMachineNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, const SDValue *Ops, unsigned NumOps) argument
5311 getNodeIfExists(unsigned Opcode, SDVTList VTList, const SDValue *Ops, unsigned NumOps) argument
[all...]
/macosx-10.10.1/JavaScriptCore-7600.1.17/bytecode/
H A DOpcode.h83 typedef void* Opcode; typedef in namespace:JSC
85 typedef OpcodeID Opcode; typedef in namespace:JSC
/macosx-10.10.1/JavaScriptCore-7600.1.17/interpreter/
H A DInterpreter.h40 #include "Opcode.h"
209 Opcode getOpcode(OpcodeID id)
219 OpcodeID getOpcodeID(Opcode opcode)
230 bool isOpcode(Opcode);
267 bool isCallBytecode(Opcode opcode) { return opcode == getOpcode(op_call) || opcode == getOpcode(op_construct) || opcode == getOpcode(op_call_eval); }
278 Opcode* m_opcodeTable; // Maps OpcodeID => Opcode for compiling
279 HashMap<Opcode, OpcodeID> m_opcodeIDTable; // Maps Opcode => OpcodeID for decompiling
/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/
H A DInstruction.h96 static inline bool isBinaryOp(unsigned Opcode) { argument
97 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd;
100 /// @brief Determine if the Opcode is one of the shift instructions.
101 static inline bool isShift(unsigned Opcode) { argument
102 return Opcode >= Shl && Opcode <= AShr;

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