Searched refs:isSExt (Results 1 - 16 of 16) sorted by relevance
| /macosx-10.10/llvmCore-3425.0.34/include/llvm/Target/ |
| H A D | TargetCallingConv.h | 57 bool isSExt() const { return Flags & SExt; } function in struct:llvm::ISD::ArgFlagsTy
|
| H A D | TargetLowering.h | 1273 bool isSExt : 1;
1281 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
|
| /macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 906 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; local
909 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
915 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
921 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
926 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
940 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; local
943 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
949 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
955 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
960 case MVT::i32: Opcode = isSExt
[all...] |
| H A D | PPCISelLowering.cpp | 2179 if (Flags.isSExt())
3327 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
|
| /macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.cpp | 166 Entry.isSExt = false;
178 Entry.isSExt = true;
|
| H A D | ARMFastISel.cpp | 2136 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
|
| /macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypes.cpp | 1077 Entry.isSExt = isSigned;
1111 Entry.isSExt = isSigned;
|
| H A D | SelectionDAGBuilder.cpp | 718 bool isSExt = true; local
721 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
723 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
725 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
727 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
729 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
731 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
733 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
735 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
741 Parts[i] = DAG.getNode(isSExt
[all...] |
| H A D | LegalizeDAG.cpp | 1854 Entry.isSExt = isSigned;
1903 Entry.isSExt = isSigned;
1937 Entry.isSExt = isSigned;
2063 Entry.isSExt = isSigned;
2072 Entry.isSExt = isSigned;
|
| H A D | LegalizeIntegerTypes.cpp | 2316 Entry.isSExt = true;
2324 Entry.isSExt = true;
|
| H A D | SelectionDAG.cpp | 3916 Entry.isSExt = true;
3920 Entry.isSExt = false;
|
| /macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 783 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
789 if (Outs[0].Flags.isSExt())
1655 if (Flags.isSExt())
|
| /macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 137 if (ArgFlags.isSExt())
212 if (ArgFlags.isSExt())
|
| /macosx-10.10/llvmCore-3425.0.34/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 499 else if (Outs[i].Flags.isSExt())
|
| /macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/ |
| H A D | SPUISelLowering.cpp | 70 Entry.isSExt = isSigned;
|
| /macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2547 if (ArgFlags.isSExt())
|
Completed in 250 milliseconds