Searched refs:i16 (Results 1 - 25 of 62) sorted by relevance

123

/macosx-10.10/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp267 MVT::i16, AM.Disp,
270 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
273 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
275 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
280 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
316 case MVT::i16:
341 case MVT::i16:
349 VT, MVT::i16, MVT::Other,
364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
370 VT, MVT::i16, MV
[all...]
H A DMSP430ISelLowering.cpp68 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
99 setOperationAction(ISD::SHL, MVT::i16, Custom);
100 setOperationAction(ISD::SRL, MVT::i16, Custom);
103 setOperationAction(ISD::ROTL, MVT::i16, Expand);
104 setOperationAction(ISD::ROTR, MVT::i16, Expand);
105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custo
[all...]
/macosx-10.10/MITKerberosShim-66/test/
H A Dtest-kClient.c39 UInt16 *i16 = NULL; local
73 KClientGetVersion(i16, i16, (const char**)&cbuffer));
/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUISelLowering.cpp43 if (VT==MVT::i16) retval=2;
106 addRegisterClass(MVT::i16, &SPU::R16CRegClass);
113 // SPU has no sign or zero extended loads for i1, i8, i16:
123 setTruncStoreAction(MVT::i128, MVT::i16, Expand);
169 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
184 setOperationAction(ISD::SREM, MVT::i16, Expand);
185 setOperationAction(ISD::UREM, MVT::i16, Expand);
186 setOperationAction(ISD::SDIV, MVT::i16, Expand);
187 setOperationAction(ISD::UDIV, MVT::i16, Expand);
188 setOperationAction(ISD::SDIVREM, MVT::i16, Expan
[all...]
H A DSPUISelDAGToDAG.cpp54 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
61 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
82 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
182 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
317 EVT OffsVT = MVT::i16;
578 case MVT::i16:
661 case MVT::i16:
914 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
1063 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
/macosx-10.10/dtrace-147/test/tst/common/typedef/
H A Dtst.TypedefDataAssign.d85 new_int16 i16;
/macosx-10.10/ICU-531.30/icuSources/test/iotest/
H A Diotest.cpp212 int16_t i16; local
268 i16 = (int16_t)uto64(argument);
269 uBufferLenReturned = u_sprintf_u(uBuffer, format, i16);
270 uFileBufferLenReturned = u_fprintf_u(testFile.getAlias(), format, i16);
377 int16_t i16, expected16; local
451 uBufferLenReturned = u_sscanf_u(argument, format, &i16);
452 //uFileBufferLenReturned = u_fscanf_u(testFile, format, i16);
453 if (i16 != expected16) {
455 i, i16, expected16);
581 int16_t i16; local
[all...]
H A Dstrtst.c748 int16_t i16 = -1; local
758 if (u_sscanf(testStr, "%*4[123]%hn%*[1-9]", &i16) != 0) {
761 if (i16 != 4) {
762 log_err("test 2: scanf returned %d instead of 4\n", i16);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp98 VT = MVT::i16;
121 VT = MVT::i16;
H A DARMFastISel.cpp558 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
776 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
904 case MVT::i16:
1027 case MVT::i16:
1151 case MVT::i16:
1417 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1453 case MVT::i16:
1480 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1593 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1600 if (SrcVT == MVT::i16 || SrcV
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp212 case MVT::i16: Opcode = NVPTX::LD_i16_avar; break;
242 case MVT::i16: Opcode = NVPTX::LD_i16_asi; break;
272 case MVT::i16: Opcode = NVPTX::LD_i16_ari; break;
301 case MVT::i16: Opcode = NVPTX::LD_i16_areg; break;
398 case MVT::i16: Opcode = NVPTX::ST_i16_avar; break;
429 case MVT::i16: Opcode = NVPTX::ST_i16_asi; break;
460 case MVT::i16: Opcode = NVPTX::ST_i16_ari; break;
489 case MVT::i16: Opcode = NVPTX::ST_i16_areg; break;
/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DValueTypes.h41 i16 = 3, // This is a 16 bit integer value enumerator in enum:llvm::MVT::SimpleValueType
68 v1i16 = 22, // 1 x i16
69 v2i16 = 23, // 2 x i16
70 v4i16 = 24, // 4 x i16
71 v8i16 = 25, // 8 x i16
72 v16i16 = 26, // 16 x i16
267 case v16i16: return i16;
339 case i16 :
418 return MVT::i16;
445 case MVT::i16
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/macosx-10.10/cxxfilt-11/cxxfilt/include/opcode/
H A Dcrx.h121 i16, i32, enumerator in enum:__anon7983
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonVarargsCallingConvention.h49 LocVT == MVT::i16 ||
H A DHexagonISelLowering.cpp134 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
209 LocVT == MVT::i16) {
598 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
846 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1143 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1144 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1145 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1146 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1280 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1285 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Lega
[all...]
H A DHexagonISelDAGToDAG.cpp284 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
321 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
510 } else if (LoadedVT == MVT::i16) {
616 else if (StoredVT == MVT::i16) Opcode = Hexagon::POST_SThri;
642 else if (StoredVT == MVT::i16) Opcode = Hexagon::STrih;
696 else if (StoredVT == MVT::i16) Opcode = Hexagon::STrih_indexed;
824 if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
829 // i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
853 // i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
/macosx-10.10/llvmCore-3425.0.34/include/llvm/Support/
H A DDataTypes.h.cmake143 # define INT16_C(C) C##i16
H A DDataTypes.h.in140 # define INT16_C(C) C##i16
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp909 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
915 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
921 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
926 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
943 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
949 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
955 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
961 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp95 AVT = MVT::i16;
209 AVT = MVT::i16;
H A DX86ISelDAGToDAG.cpp611 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
614 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1309 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1311 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1666 // A special case for i16, which needs truncating as, in most cases, it's
1669 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1730 case MVT::i16:
1870 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1934 if (LdVT == MVT::i16) return X86::DEC16m;
1940 if (LdVT == MVT::i16) retur
[all...]
H A DX86FastISel.cpp190 case MVT::i16:
252 case MVT::i16: Opc = X86::MOV16mr; break;
296 case MVT::i16: Opc = X86::MOV16mi; break;
780 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
862 case MVT::i16: return X86::CMP16rr;
880 case MVT::i16: return X86::CMP16ri;
1121 case MVT::i16: TestOpc = X86::TEST16ri; break;
1240 if (VT == MVT::i16) {
1333 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) ?
1374 VT = MVT::i16;
[all...]
H A DX86ISelLowering.cpp167 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
225 addRegisterClass(MVT::i16, &X86::GR16RegClass);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
272 // SSE has no i16 to fp conversion, only i32
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promot
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/VMCore/
H A DValueTypes.cpp117 case MVT::i16: return "i16";
177 case MVT::i16: return Type::getInt16Ty(Context);
/macosx-10.10/smb-759.0/kernel/netsmb/
H A Dsmb_crypt.c1271 uint16_t i16; local
1344 i16 = htoles(SMB2_ENCRYPTION_AES128_CCM);
1345 memcpy(msgp + SMB3_AES_TF_ENCR_ALG_OFF, &i16,
1405 uint16_t i16; local
1456 i16 = letohs(tf_hdr->encrypt_algorithm);
1457 if (i16 != SMB2_ENCRYPTION_AES128_CCM) {
1458 SMBDEBUG("Unsupported ENCR alg: %u\n", (uint32_t)i16);

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