/macosx-10.10/Heimdal-398.1.2/lib/hcrypto/ |
H A D | sha256.c | 42 #define ROTR(x,n) (((x)>>(n)) | ((x) << (32 - (n)))) macro 44 #define Sigma0(x) (ROTR(x,2) ^ ROTR(x,13) ^ ROTR(x,22)) 45 #define Sigma1(x) (ROTR(x,6) ^ ROTR(x,11) ^ ROTR(x,25)) 46 #define sigma0(x) (ROTR(x,7) ^ ROTR(x,18) ^ ((x)>>3)) 47 #define sigma1(x) (ROTR( [all...] |
H A D | sha512.c | 42 #define ROTR(x,n) (((x)>>(n)) | ((x) << (64 - (n)))) macro 44 #define Sigma0(x) (ROTR(x,28) ^ ROTR(x,34) ^ ROTR(x,39)) 45 #define Sigma1(x) (ROTR(x,14) ^ ROTR(x,18) ^ ROTR(x,41)) 46 #define sigma0(x) (ROTR(x,1) ^ ROTR(x,8) ^ ((x)>>7)) 47 #define sigma1(x) (ROTR( [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 29 case ISD::ROTR: return ARM_AM::ror; 30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
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H A D | ARMISelLowering.cpp | 8775 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, N0, N1);
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/macosx-10.10/tcl-105/tcl_ext/tcllib/tcllib/modules/sha1/ |
H A D | sha256.c | 69 #define ROTR(x, n) (((x) >> (n)) | ((x) << (32 - (n)))) macro 73 #define SIGMA0(x) (ROTR((x), 2) ^ ROTR((x), 13) ^ ROTR((x), 22)) 74 #define SIGMA1(x) (ROTR((x), 6) ^ ROTR((x), 11) ^ ROTR((x), 25)) 75 #define sigma0(x) (ROTR((x), 7) ^ ROTR((x), 18) ^ ((x) >> 3)) 76 #define sigma1(x) (ROTR(( [all...] |
/macosx-10.10/OpenSSL098-52/src/crypto/sha/ |
H A D | sha512.c | 317 # define ROTR(a,n) ({ unsigned long ret; \ macro 347 # define ROTR(a,n) ({ unsigned long ret; \ macro 354 # define ROTR(a,n) _rotr64((a),n) macro 389 #ifndef ROTR 390 #define ROTR(x,s) (((x)>>s) | (x)<<(64-s)) macro 393 #define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) 394 #define Sigma1(x) (ROTR((x),14) ^ ROTR(( [all...] |
/macosx-10.10/OpenSSL098-52/src/crypto/sha/asm/ |
H A D | sha512-ia64.pl | 220 _rotr r11=$t1,$Sigma1[0] } // ROTR(e,14) 453 _rotr r11=$t1,$Sigma1[0] } // ROTR(e,14) 459 _rotr r8=$t1,$Sigma1[1] } // ROTR(e,18) 463 _rotr r9=$t1,$Sigma1[2] } // ROTR(e,41) 467 _rotr r10=$t0,$Sigma0[0] } // ROTR(a,28) 471 _rotr r11=$t0,$Sigma0[1] } // ROTR(a,34) 475 _rotr r8=$t0,$Sigma0[2] } // ROTR(a,39) 493 _rotr r8=X[15-1],$sigma0[0] } // ROTR(s0,1) 497 _rotr r9=X[15-1],$sigma0[1] } // ROTR(s0,8) 502 _rotr r10=X[15-14],$sigma1[0] };;// ROTR(s [all...] |
/macosx-10.10/vim-55/src/ |
H A D | sha256.c | 86 #define ROTR(x, n) (SHR(x, n) | (x << (32 - n))) macro 88 #define S0(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3)) 89 #define S1(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHR(x, 10)) 91 #define S2(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) 92 #define S3(x) (ROTR(x, 6) ^ ROTR( [all...] |
/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 316 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 136 setOperationAction(ISD::ROTR , MVT::i64, Legal); 140 setOperationAction(ISD::ROTR , MVT::i64, Expand); 144 setOperationAction(ISD::ROTR , MVT::i32, Legal); 148 setOperationAction(ISD::ROTR , MVT::i32, Expand); 152 setOperationAction(ISD::ROTR , MVT::i16, Expand); 154 setOperationAction(ISD::ROTR , MVT::i8, Expand);
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/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 175 case ISD::ROTR: return "rotr";
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H A D | LegalizeVectorOps.cpp | 191 case ISD::ROTR:
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H A D | SelectionDAG.cpp | 2232 case ISD::ROTR: 2237 if (Op.getOpcode() == ISD::ROTR) 2731 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2856 case ISD::ROTR: 6024 case ISD::ROTR:
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H A D | DAGCombiner.cpp | 3007 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3008 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3184 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3225 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3259 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3272 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3298 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3312 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
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H A D | LegalizeIntegerTypes.cpp | 798 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 2470 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
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H A D | LegalizeDAG.cpp | 1273 case ISD::ROTR:
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 231 // FIXME: Change from "expand" to appropriate type once ROTR is supported in 233 setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/); 234 setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/); 235 setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/); 2232 case ISD::ROTR: 2813 case ISD::ROTR:
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 102 setOperationAction(ISD::ROTR, MVT::i8, Expand); 104 setOperationAction(ISD::ROTR, MVT::i16, Expand);
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 165 setOperationAction(ISD::ROTR, MVT::i32, Expand);
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 774 setOperationAction(ISD::ROTR , MVT::i32, Expand);
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1373 setOperationAction(ISD::ROTR , MVT::i32, Expand);
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 110 setOperationAction(ISD::ROTR , MVT::i32, Expand);
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 253 setOperationAction(ISD::ROTR, MVT::i32, Expand); 256 setOperationAction(ISD::ROTR, MVT::i64, Expand);
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 167 // PowerPC does not have ROTR 168 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 169 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 764 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
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