Searched refs:RCI (Results 1 - 12 of 12) sorted by relevance

/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/
H A DRegisterClassInfo.cpp76 RCInfo &RCI = RegClass[RC->getID()]; local
81 if (!RCI.Order)
82 RCI.Order.reset(new unsigned[NumRegs]);
99 RCI.Order[N++] = PhysReg;
101 RCI.NumRegs = N + CSRAlias.size();
102 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
105 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
108 if (StressRA && RCI.NumRegs > StressRA)
109 RCI.NumRegs = StressRA;
113 if (Super != RC && getNumAllocatableRegs(Super) > RCI
[all...]
H A DAllocationOrder.h29 const RegisterClassInfo &RCI; member in class:llvm::AllocationOrder
H A DAllocationOrder.cpp28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
66 ArrayRef<unsigned> O = RCI.getOrder(RC);
H A DAggressiveAntiDepBreaker.h134 const RegisterClassInfo &RCI,
H A DPostRASchedulerList.cpp198 AliasAnalysis *AA, const RegisterClassInfo &RCI,
214 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
216 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
196 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) argument
H A DCriticalAntiDepBreaker.cpp30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : argument
35 RegClassInfo(RCI),
H A DAggressiveAntiDepBreaker.cpp118 const RegisterClassInfo &RCI,
124 RegClassInfo(RCI),
117 AggressiveAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector& CriticalPathRCs) argument
H A DRegisterPressure.cpp174 RCI = rci;
/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DRegisterClassInfo.h65 const RCInfo &RCI = RegClass[RC->getID()]; local
66 if (Tag != RCI.Tag)
68 return RCI;
H A DRegisterPressure.h138 const RegisterClassInfo *RCI; member in class:llvm::RegPressureTracker
165 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {}
168 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {}
/macosx-10.10/llvmCore-3425.0.34/lib/Target/
H A DTargetRegisterInfo.cpp180 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
181 if (RCI.getSubReg() == Idx)
184 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp723 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
724 SuperRegRC.setBitsInMask(RCI.getMask());
2835 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2836 E = RI->regclass_end(); RCI != E; ++RCI) {
2837 const TargetRegisterClass *RC = *RCI;

Completed in 208 milliseconds