Searched refs:LR (Results 1 - 25 of 59) sorted by relevance

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/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/
H A DLiveIntervalAnalysis.cpp239 LiveRange LR(defIndex, killIdx, ValNo);
240 interval.addRange(LR);
241 DEBUG(dbgs() << " +" << LR << "\n");
268 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
270 interval.addRange(LR);
271 DEBUG(dbgs() << " +" << LR);
289 LiveRange LR(Start, killIdx, ValNo);
290 interval.addRange(LR);
291 DEBUG(dbgs() << " +" << LR);
336 LiveRange LR(DefInde
1134 const LiveRange& LR = *LRI; local
1192 LiveRange* LR = LI->getLiveRangeContaining(OldIdx); local
1197 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot()); local
1214 LiveRange* LR = EI->second; local
1221 LiveRange* LR = II->second; local
1232 LiveRange* LR = EI->second; local
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H A DLiveInterval.cpp276 LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
277 SlotIndex Start = LR.start, End = LR.end;
281 // another interval, just extend that interval to contain the range of LR.
284 if (LR.valno == B->valno) {
301 if (LR.valno == it->valno) {
305 // If LR is a complete superset of an interval, we may need to grow its
321 return ranges.insert(it, LR);
665 iterator LR = I++;
666 if (LR
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H A DRegAllocFast.cpp217 void RAFast::addKillFlag(const LiveReg &LR) { argument
218 if (!LR.LastUse) return;
219 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
220 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
221 if (MO.getReg() == LR.PhysReg)
224 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
261 LiveReg &LR local
483 assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) argument
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H A DExecutionDepsFix.cpp578 const LiveReg &LR = LiveRegs[rx]; local
580 if (!LR.Value->getCommonDomains(available)) {
588 if (LR.Def < i->Def) {
590 Regs.insert(i, LR);
594 Regs.push_back(LR);
/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DLiveInterval.h108 bool operator<(const LiveRange &LR) const {
109 return start < LR.start || (start == LR.start && end < LR.end);
111 bool operator==(const LiveRange &LR) const {
112 return start == LR.start && end == LR.end;
121 raw_ostream& operator<<(raw_ostream& os, const LiveRange &LR);
124 inline bool operator<(SlotIndex V, const LiveRange &LR) {
125 return V < LR
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUFrameLowering.h27 std::pair<unsigned, int> LR[1]; member in class:llvm::SPUFrameLowering
69 //! Minimum frame size (enough to spill LR + SP)
H A DSPUTargetMachine.cpp31 return &LR[0];
H A DSPUFrameLowering.cpp37 LR[0].first = SPU::R0;
38 LR[0].second = 16;
243 // Mark LR and SP unused, since the prolog spills them to stack and
/macosx-10.10/zsh-61/zsh/Src/
H A Dmath.c73 /* LR = left-to-right associativity *
77 #define LR 0x0000 macro
289 /* 0 */ LR, LR|OP_OP|OP_OPF, RL, RL, RL|OP_OP|OP_OPF,
290 /* 5 */ RL|OP_OP|OP_OPF, RL, RL, LR|OP_A2IO, LR|OP_A2IO,
291 /* 10 */ LR|OP_A2IO, LR|OP_A2, LR|OP_A2, LR|OP_A2I
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/XCore/
H A DXCoreFrameLowering.cpp128 MBB.addLiveIn(XCore::LR);
149 MachineLocation CSSrc(XCore::LR);
155 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
156 MBB.addLiveIn(XCore::LR);
162 MachineLocation CSSrc(XCore::LR);
255 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII);
342 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
346 MF.getRegInfo().setPhysRegUnused(XCore::LR);
351 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
H A DXCoreRegisterInfo.cpp41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
66 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
79 Reserved.set(XCore::LR);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/XCore/MCTargetDesc/
H A DXCoreMCTargetDesc.cpp42 InitXCoreMCRegisterInfo(X, XCore::LR);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp58 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
324 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
331 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
336 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
343 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
348 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
360 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
367 ARM::R1, ARM::R3, ARM::R12,ARM::LR, AR
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H A DARMFrameLowering.cpp180 case ARM::LR:
600 // Add the callee-saved register as live-in unless it's LR and
601 // @llvm.returnaddress is called. If LR is returned for
605 if (Reg == ARM::LR) {
671 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
702 // If we adjusted the reg to PC from LR above, switch it back here. We
705 Regs[0] = ARM::LR;
1224 // Spill LR if Thumb1 function uses variable length argument lists.
1226 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1264 if (Reg == ARM::LR)
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H A DThumb1FrameLowering.cpp91 case ARM::LR:
267 // to LR, and we can't pop the value directly to the PC since
269 // pop the old LR into R3 as a temporary.
274 // Epilogue for vararg functions: pop LR to R3 and branch off it.
310 // Add the callee-saved register as live-in unless it's LR and
311 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
313 if (Reg == ARM::LR) {
349 if (Reg == ARM::LR) {
H A DARMBaseRegisterInfo.h43 case LR: case SP: case PC:
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/AsmParser/
H A DARMAsmLexer.cpp119 .Case("r14", ARM::LR)
/macosx-10.10/cxxfilt-11/cxxfilt/opcodes/
H A Dmcore-opc.h24 OMa, SI, I7, LS, BR, BL, LR, LJ, enumerator in enum:__anon8073
160 { "lrw", LR, 0, 0x7000 },
H A Dmcore-dis.c43 /* LR */ 0xF000,
226 case LR:
/macosx-10.10/zsh-61/zsh/Functions/Misc/
H A Dsticky-note51 emulate -LR zsh
/macosx-10.10/llvmCore-3425.0.34/include/llvm/ADT/
H A DImmutableSet.h502 TreeTy *LR = getRight(L); local
504 if (getHeight(LL) >= getHeight(LR))
505 return createNode(LL, L, createNode(LR,V,R));
507 assert(!isEmpty(LR) && "LR cannot be empty because it has a height >= 1");
509 TreeTy *LRL = getLeft(LR);
510 TreeTy *LRR = getRight(LR);
512 return createNode(createNode(LL,L,LRL), LR, createNode(LRR,V,R));
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp47 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp147 InitARMMCRegisterInfo(X, ARM::LR);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp307 // Check if the link register (LR) must be saved.
467 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
506 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
570 // Check if the link register (LR) has been saved.
749 /// MustSaveLR - Return true if this function requires that we save the LR
752 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { argument
755 // We need a save/restore of LR if there is any def of LR (which is
757 // some use of the LR stack slot (e.g. for builtin_return_address).
758 // (LR come
770 unsigned LR = RegInfo->getRARegister(); local
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/macosx-10.10/tcl-105/tcl_ext/tklib/tklib/modules/widget/
H A Ddateentry.tcl61 R0lGODlhEAAQAPZ8AP99O/9/PWmrYmytZW6uaHOxbP+EQv+LR/+QTf+UUv+VVP+WVP+

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