/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_gt_pm_irq.h | 19 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask);
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H A D | intel_gt_pm_irq.c | 62 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask) argument 69 intel_uncore_write(uncore, reg, reset_mask); 70 intel_uncore_write(uncore, reg, reset_mask);
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H A D | intel_reset.c | 412 u32 *reset_mask, 499 *reset_mask |= sfc_lock.reset_bit; 528 u32 reset_mask, unlock_mask = 0; local 532 reset_mask = GEN11_GRDOM_FULL; 534 reset_mask = 0; 536 reset_mask |= engine->reset_domain; 537 ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask); 543 ret = gen6_hw_domain_reset(gt, reset_mask); 784 intel_engine_mask_t reset_mask; local 786 reset_mask 411 gen11_lock_sfc(struct intel_engine_cs *engine, u32 *reset_mask, u32 *unlock_mask) argument [all...] |
/linux-master/drivers/clk/sunxi/ |
H A D | clk-usb.c | 81 u32 reset_mask; member in struct:usb_clk_data 144 if (data->reset_mask == 0) 162 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; 170 .reset_mask = BIT(2) | BIT(1) | BIT(0), 183 .reset_mask = BIT(1) | BIT(0), 194 .reset_mask = BIT(2) | BIT(1) | BIT(0), 205 .reset_mask = BIT(2) | BIT(1) | BIT(0), 217 .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), 228 .reset_mask = BIT(19) | BIT(18) | BIT(17), 242 .reset_mask [all...] |
/linux-master/drivers/reset/ |
H A D | reset-ti-sci.c | 20 * @reset_mask: reset mask to use for toggling reset 21 * @lock: synchronize reset_mask read-modify-writes 25 u32 reset_mask; member in struct:ti_sci_reset_control 83 reset_state |= control->reset_mask; 85 reset_state &= ~control->reset_mask; 161 return reset_state & control->reset_mask; 198 control->reset_mask = reset_spec->args[1];
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/linux-master/drivers/clk/ |
H A D | clk-twl6040.c | 33 const u8 reset_mask = TWL6040_HPLLRST; /* Same for HPPLL and LPPLL */ local 36 ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask); 40 ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask);
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | ni.c | 1722 u32 reset_mask = 0; local 1733 reset_mask |= RADEON_RESET_GFX; 1737 reset_mask |= RADEON_RESET_CP; 1740 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1745 reset_mask |= RADEON_RESET_DMA; 1750 reset_mask |= RADEON_RESET_DMA1; 1755 reset_mask |= RADEON_RESET_DMA; 1758 reset_mask |= RADEON_RESET_DMA1; 1763 reset_mask |= RADEON_RESET_RLC; 1766 reset_mask | 1798 cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) argument 1932 u32 reset_mask; local 1967 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); local [all...] |
H A D | evergreen_dma.c | 172 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); local 174 if (!(reset_mask & RADEON_RESET_DMA)) {
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H A D | si_dma.c | 42 u32 reset_mask = si_gpu_check_soft_reset(rdev); local 50 if (!(reset_mask & mask)) {
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H A D | r600.c | 1617 u32 reset_mask = 0; local 1628 reset_mask |= RADEON_RESET_GFX; 1635 reset_mask |= RADEON_RESET_GFX; 1640 reset_mask |= RADEON_RESET_CP; 1643 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1648 reset_mask |= RADEON_RESET_DMA; 1653 reset_mask |= RADEON_RESET_RLC; 1656 reset_mask |= RADEON_RESET_IH; 1659 reset_mask |= RADEON_RESET_SEM; 1662 reset_mask | 1684 r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) argument 1883 u32 reset_mask; local 1923 u32 reset_mask = r600_gpu_check_soft_reset(rdev); local [all...] |
H A D | si.c | 3756 u32 reset_mask = 0; local 3767 reset_mask |= RADEON_RESET_GFX; 3771 reset_mask |= RADEON_RESET_CP; 3774 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 3779 reset_mask |= RADEON_RESET_RLC; 3784 reset_mask |= RADEON_RESET_DMA; 3789 reset_mask |= RADEON_RESET_DMA1; 3794 reset_mask |= RADEON_RESET_DMA; 3797 reset_mask |= RADEON_RESET_DMA1; 3803 reset_mask | 3835 si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) argument 4069 u32 reset_mask; local 4109 u32 reset_mask = si_gpu_check_soft_reset(rdev); local [all...] |
H A D | r600_dma.c | 209 u32 reset_mask = r600_gpu_check_soft_reset(rdev); local 211 if (!(reset_mask & RADEON_RESET_DMA)) {
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H A D | ni_dma.c | 288 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); local 296 if (!(reset_mask & mask)) {
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H A D | evergreen.c | 3827 u32 reset_mask = 0; local 3837 reset_mask |= RADEON_RESET_GFX; 3841 reset_mask |= RADEON_RESET_CP; 3844 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 3849 reset_mask |= RADEON_RESET_DMA; 3854 reset_mask |= RADEON_RESET_DMA; 3859 reset_mask |= RADEON_RESET_RLC; 3862 reset_mask |= RADEON_RESET_IH; 3865 reset_mask |= RADEON_RESET_SEM; 3868 reset_mask | 3894 evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) argument 4052 u32 reset_mask; local 4092 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); local [all...] |
H A D | cik.c | 4844 u32 reset_mask = 0; local 4855 reset_mask |= RADEON_RESET_GFX; 4858 reset_mask |= RADEON_RESET_CP; 4863 reset_mask |= RADEON_RESET_RLC; 4868 reset_mask |= RADEON_RESET_DMA; 4873 reset_mask |= RADEON_RESET_DMA1; 4878 reset_mask |= RADEON_RESET_DMA; 4881 reset_mask |= RADEON_RESET_DMA1; 4887 reset_mask |= RADEON_RESET_IH; 4890 reset_mask | 4922 cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) argument 5211 u32 reset_mask; local 5251 u32 reset_mask = cik_gpu_check_soft_reset(rdev); local [all...] |
H A D | cik_sdma.c | 776 u32 reset_mask = cik_gpu_check_soft_reset(rdev); local 784 if (!(reset_mask & mask)) {
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/linux-master/drivers/net/ethernet/ibm/ |
H A D | ibmveth.h | 73 unsigned long reset_mask, unsigned long set_mask, 80 reset_mask, set_mask); 72 h_illan_attributes(unsigned long unit_address, unsigned long reset_mask, unsigned long set_mask, unsigned long *ret_attributes) argument
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/linux-master/drivers/misc/cxl/ |
H A D | hcalls.h | 165 * Set reset_mask = 1 to reset PSL errors 168 u64 control_mask, u64 reset_mask);
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H A D | hcalls.c | 436 * Set reset_mask = 1 to reset PSL errors 439 u64 control_mask, u64 reset_mask) 448 control_mask, reset_mask); 450 unit_address, process_token, control_mask, reset_mask, 453 control_mask, reset_mask, retbuf[0], rc); 438 cxl_h_control_faults(u64 unit_address, u64 process_token, u64 control_mask, u64 reset_mask) argument
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H A D | trace.h | 610 u64 control_mask, u64 reset_mask, unsigned long r4, 614 control_mask, reset_mask, r4, rc), 620 __field(u64, reset_mask) 629 __entry->reset_mask = reset_mask; 635 "control_mask=%#llx reset_mask=%#llx r4=%#lx rc=%li", 639 __entry->reset_mask,
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/linux-master/drivers/watchdog/ |
H A D | aspeed_wdt.c | 407 u32 reset_mask[2]; local 427 ret = of_property_read_u32_array(np, "aspeed,reset-mask", reset_mask, nrstmask); 429 writel(reset_mask[0], wdt->base + WDT_RESET_MASK1); 431 writel(reset_mask[1], wdt->base + WDT_RESET_MASK2);
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/linux-master/drivers/crypto/intel/qat/qat_common/ |
H A D | qat_hal.c | 304 unsigned int reset_mask = handle->chip_info->icp_rst_mask; local 309 csr_val |= reset_mask; 476 unsigned int reset_mask = handle->chip_info->icp_rst_mask; local 485 csr_val &= ~reset_mask; 491 csr_val &= reset_mask; 495 csr_val |= reset_mask;
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/linux-master/sound/soc/tegra/ |
H A D | tegra210_i2s.c | 90 unsigned int reset_mask = I2S_SOFT_RESET_MASK; local 112 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en); 115 !(val & reset_mask & reset_en),
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/linux-master/drivers/net/ethernet/smsc/ |
H A D | smsc911x.c | 1449 unsigned int reset_mask = HW_CFG_SRST_; local 1479 reset_mask = RESET_CTL_DIGITAL_RST_; 1483 smsc911x_reg_write(pdata, reset_offset, reset_mask); 1490 } while ((--timeout) && (temp & reset_mask)); 1492 if (unlikely(temp & reset_mask)) {
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/linux-master/drivers/net/wireless/ath/ath10k/ |
H A D | htt_tx.c | 631 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, argument 659 memcpy(req->reset_types, &reset_mask, 3);
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