Searched refs:odiv (Results 1 - 7 of 7) sorted by relevance

/linux-master/drivers/clk/imx/
H A Dclk-fracn-gppll.c53 .odiv = (_odiv), \
63 .odiv = (_odiv), \
76 * Fout = Fvco / odiv
101 * Fout = Fvco / odiv
156 u32 mfi, mfn, mfd, rdiv, odiv; local
171 odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
182 rate_table[i].odiv == odiv)
192 switch (odiv) {
194 odiv
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H A Dclk.h86 unsigned int odiv; member in struct:imx_fracn_gppll_rate_table
/linux-master/drivers/media/dvb-frontends/
H A Dstb6100.c302 int psd2, odiv; local
310 odiv = (regs[STB6100_VCO] & STB6100_VCO_ODIV) >> STB6100_VCO_ODIV_SHIFT;
315 *frequency = state->frequency = fvco >> (odiv + 1);
318 "frequency = %u kHz, odiv = %u, psd2 = %u, fxtal = %u kHz, fvco = %u kHz, N(I) = %u, N(F) = %u",
319 state->frequency, odiv, psd2, state->reference, fvco, nint, nfrac);
333 u8 g, psd2, odiv; local
358 odiv = 1;
360 odiv = 0;
363 regs[STB6100_VCO] = 0xe0 | (odiv << STB6100_VCO_ODIV_SHIFT);
384 fvco = frequency << (1 + odiv);
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/linux-master/drivers/clk/
H A Dclk-hsdk-pll.c50 u32 odiv; member in struct:hsdk_pll_cfg
143 val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
172 u32 idiv, fbdiv, odiv; local
191 /* output divider = 2^(reg.odiv) */
192 odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
195 do_div(rate, idiv * odiv);
/linux-master/drivers/clk/axs10x/
H A Dpll_clock.c70 u32 odiv; member in struct:axs10x_pll_cfg
139 u32 idiv, fbdiv, odiv; local
144 odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));
147 do_div(rate, idiv * odiv);
187 axs10x_encode_div(pll_cfg[i].odiv, 1));
H A Di2s_pll_clock.c102 unsigned int idiv, fbdiv, odiv; local
106 odiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_ODIV0_REG));
108 return ((parent_rate / idiv) * fbdiv) / odiv;
/linux-master/drivers/clk/microchip/
H A Dclk-core.c591 static inline u32 spll_odiv_to_divider(u32 odiv) argument
593 odiv = clamp_val(odiv, PLL_ODIV_MIN, PLL_ODIV_MAX);
595 return 1 << odiv;
649 u32 mult, odiv, div, v; local
653 odiv = ((v >> PLL_ODIV_SHIFT) & PLL_ODIV_MASK);
655 div = spll_odiv_to_divider(odiv);
681 u32 mult, odiv, v; local
684 ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv);
705 v |= (mult << PLL_MULT_SHIFT) | (odiv << PLL_ODIV_SHIF
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