Searched refs:mmTPC0_CFG_WR_RATE_LIMIT (Results 1 - 2 of 2) sorted by relevance

/linux-master/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dtpc0_cfg_regs.h598 #define mmTPC0_CFG_WR_RATE_LIMIT 0xE06950 macro
/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi_security.c9589 mask |= 1U << ((mmTPC0_CFG_WR_RATE_LIMIT & 0x7F) >> 2);

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