Searched refs:IO_IRQ_BASE (Results 1 - 4 of 4) sorted by relevance

/linux-master/arch/mips/include/asm/dec/
H A Dioasic_ints.h66 #define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */ macro
69 #define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE)
/linux-master/drivers/irqchip/
H A Dirq-zevio.c26 #define IO_IRQ_BASE 0x000 macro
92 zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE);
109 gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE;
110 gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE;
111 gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE;
112 gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET;
/linux-master/arch/mips/dec/
H A Dint-handler.S250 li a0,IO_IRQ_BASE
259 li a0,IO_IRQ_BASE+IO_INR_DMA
H A Dsetup.c502 init_ioasic_irqs(IO_IRQ_BASE);
599 init_ioasic_irqs(IO_IRQ_BASE);
700 init_ioasic_irqs(IO_IRQ_BASE);

Completed in 149 milliseconds