Searched refs:IMX8ULP_CLK_SPLL3_PFD3_DIV1 (Results 1 - 3 of 3) sorted by relevance

/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx8ulp-clock.h28 #define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 macro
/linux-master/include/dt-bindings/clock/
H A Dimx8ulp-clock.h28 #define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 macro
/linux-master/drivers/clk/imx/
H A Dclk-imx8ulp.c193 clks[IMX8ULP_CLK_SPLL3_PFD3_DIV1] = imx_clk_hw_divider("spll3_pfd3_div1", "spll3_pfd3_div1_gate", base + 0x60c, 16, 6);

Completed in 104 milliseconds