Searched refs:IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE (Results 1 - 3 of 3) sorted by relevance

/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx8ulp-clock.h81 #define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 macro
/linux-master/include/dt-bindings/clock/
H A Dimx8ulp-clock.h81 #define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 macro
/linux-master/drivers/clk/imx/
H A Dclk-imx8ulp.c271 clks[IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE] = imx_clk_hw_gate_dis("pll4_pfd0_div2_gate", "pll4_pfd0", base + 0x608, 15);

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