Searched refs:HCLK (Results 1 - 11 of 11) sorted by relevance

/linux-master/include/video/
H A Dkyro.h33 u32 HCLK; /* Hor Clock */ member in struct:kyrofb_info
/linux-master/include/dt-bindings/clock/
H A Dstm32h7-clks.h3 #define HCLK 1 macro
H A Dsamsung,s3c64xx-clock.h27 #define HCLK 8 macro
30 /* HCLK bus clocks. */
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h27 #define HCLK 8 macro
30 /* HCLK bus clocks. */
H A Dstm32h7-clks.h3 #define HCLK 1 macro
/linux-master/drivers/mmc/host/
H A Dtoshsd.h11 #define HCLK 33000000 /* 33 MHz (PCI clock) */ macro
H A Dtoshsd.c75 * SD/MMC cards at full speed (24/20MHz). HCLK (=33MHz PCI clock?) is too high
86 while (ios->clock < HCLK / div)
642 mmc->f_min = HCLK / 512;
643 mmc->f_max = HCLK;
/linux-master/drivers/clk/samsung/
H A Dclk-s3c64xx.c163 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
317 ALIAS(HCLK, NULL, "hclk"),
/linux-master/drivers/video/fbdev/kyro/
H A Dfbdev.c509 par->HCLK = (1000000000 + (lineclock / 2)) / lineclock;
/linux-master/drivers/clk/nxp/
H A Dclk-lpc32xx.c17 /* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */
91 /* System clocks, PLL 397x and HCLK PLL clocks */
213 LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
734 * DDRAM clock must be 2 times higher than HCLK,
736 * if HCLK clock rate is equal to ARM clock rate
1249 LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
/linux-master/drivers/clk/
H A Dclk-stm32h7.c517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre",

Completed in 321 milliseconds