Searched refs:DEV_CLOCK_CFG (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_port.c56 lan966x, DEV_CLOCK_CFG(port->chip_port));
122 lan966x, DEV_CLOCK_CFG(port->chip_port));
132 lan966x, DEV_CLOCK_CFG(port->chip_port));
262 lan966x, DEV_CLOCK_CFG(port->chip_port));
391 lan966x, DEV_CLOCK_CFG(port->chip_port));
570 lan966x, DEV_CLOCK_CFG(port->chip_port));
H A Dlan966x_phylink.c82 lan966x, DEV_CLOCK_CFG(port->chip_port));
H A Dlan966x_regs.h713 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) macro
/linux-master/drivers/net/ethernet/mscc/
H A Docelot.c826 DEV_CLOCK_CFG);
913 DEV_CLOCK_CFG);
933 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
955 * PORT_RST bits in DEV_CLOCK_CFG.
958 DEV_CLOCK_CFG);
H A Dvsc7514_regs.c383 REG(DEV_CLOCK_CFG, 0x0),
/linux-master/include/soc/mscc/
H A Docelot.h502 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, enumerator in enum:ocelot_reg
/linux-master/drivers/net/dsa/ocelot/
H A Dseville_vsc9953.c407 REG(DEV_CLOCK_CFG, 0x0),
H A Dfelix_vsc9959.c463 REG(DEV_CLOCK_CFG, 0x0),

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