Searched refs:DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn10/
H A Dirq_service_dcn10.c76 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn20/
H A Dirq_service_dcn20.c89 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c87 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c85 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c93 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c85 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c98 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c86 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c88 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c90 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c64 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h1120 #define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse macro

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