Searched refs:DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT (Results 1 - 14 of 14) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c60 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c56 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn10/
H A Dirq_service_dcn10.c72 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn20/
H A Dirq_service_dcn20.c85 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c83 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c81 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c89 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c81 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c94 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c82 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c84 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c86 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c60 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
/linux-master/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h1118 #define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse macro

Completed in 301 milliseconds