Searched refs:CPG_PLLECR (Results 1 - 3 of 3) sorted by relevance

/linux-master/drivers/clk/renesas/
H A Dclk-sh73a0.c28 #define CPG_PLLECR 0xd0 macro
108 if (readl(base + CPG_PLLECR) & BIT(enable_bit)) {
H A Drcar-gen3-cpg.c29 #define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */ macro
139 pll_clk->pllecr_reg = base + CPG_PLLECR;
H A Drcar-gen4-cpg.c31 #define CPG_PLLECR 0x0820 /* PLL Enable Control Register */ macro
164 pll_clk->pllecr_reg = base + CPG_PLLECR;

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