Searched refs:CLK_TOP_APLL2_DIV1 (Results 1 - 6 of 6) sorted by relevance
| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8173-clk.h | 138 #define CLK_TOP_APLL2_DIV1 128 macro
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| H A D | mediatek,mt6795-clk.h | 133 #define CLK_TOP_APLL2_DIV1 122 macro
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| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8173-clk.h | 138 #define CLK_TOP_APLL2_DIV1 128 macro
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| H A D | mediatek,mt6795-clk.h | 133 #define CLK_TOP_APLL2_DIV1 122 macro
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 519 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
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| H A D | clk-mt8173-topckgen.c | 614 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
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