Searched refs:regs (Results 1 - 25 of 223) sorted by relevance

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/haiku-fatelf/headers/private/graphics/radeon/
H A Dmmio.h14 #define INREG8( regs, addr ) (*(regs + (addr)))
16 #define OUTREG8( regs, addr, val ) do { *(regs + (addr)) = (val); } while( 0 )
18 #define INREG( regs, addr ) (*((vuint32 *)(regs + (addr))))
20 #define OUTREG( regs, addr, val ) do { *(vuint32 *)(regs + (addr)) = (val); } while( 0 )
22 #define OUTREGP( regs, addr, val, mask ) \
24 uint32 tmp = INREG( (regs), (add
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H A Dpll_access.h19 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic );
24 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic );
36 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr );
39 void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val );
42 void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask );
/haiku-fatelf/src/bin/gdb/gdb/
H A Dalphabsd-tdep.c30 alphabsd_supply_reg (char *regs, int regno) argument
33 alpha_supply_int_regs (regno, regs, regs + 31*8, NULL);
37 alphabsd_fill_reg (char *regs, int regno) argument
40 alpha_fill_int_regs (regno, regs, regs + 31*8, NULL);
H A Dhppabsd-nat.c43 const char *regs = gregs; local
47 regcache_raw_supply (regcache, regnum, regs + regnum * 4);
49 regcache_raw_supply (regcache, HPPA_SAR_REGNUM, regs);
50 regcache_raw_supply (regcache, HPPA_PCOQ_HEAD_REGNUM, regs + 32 * 4);
51 regcache_raw_supply (regcache, HPPA_PCOQ_TAIL_REGNUM, regs + 33 * 4);
61 char *regs = gregs; local
67 regcache_raw_collect (regcache, i, regs + i * 4);
71 regcache_raw_collect (regcache, HPPA_SAR_REGNUM, regs);
73 regcache_raw_collect (regcache, HPPA_PCOQ_HEAD_REGNUM, regs + 32 * 4);
75 regcache_raw_collect (regcache, HPPA_PCOQ_TAIL_REGNUM, regs
89 struct reg regs; local
107 struct reg regs; local
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H A Dm88kbsd-nat.c39 const char *regs = gregs; local
43 regcache_raw_supply (regcache, regnum, regs + regnum * 4);
53 char *regs = gregs; local
59 regcache_raw_collect (regcache, i, regs + i * 4);
71 struct reg regs;
74 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
77 m88kbsd_supply_gregset (current_regcache, &regs);
86 struct reg regs;
89 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
92 m88kbsd_collect_gregset (current_regcache, &regs, regnu
70 struct reg regs; local
85 struct reg regs; local
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H A Dppcobsd-nat.c43 struct reg regs; local
46 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
50 &regs, sizeof regs);
59 struct reg regs; local
62 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
66 regnum, &regs, sizeof regs);
69 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
H A Dvaxbsd-nat.c39 const char *regs = gregs; local
43 regcache_raw_supply (regcache, regnum, regs + regnum * 4);
53 char *regs = gregs; local
59 regcache_raw_collect (regcache, i, regs + i * 4);
71 struct reg regs;
74 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
77 vaxbsd_supply_gregset (current_regcache, &regs);
86 struct reg regs;
89 (PTRACE_TYPE_ARG3) &regs, 0) == -1)
92 vaxbsd_collect_gregset (current_regcache, &regs, regnu
70 struct reg regs; local
85 struct reg regs; local
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H A Dshnbsd-tdep.c59 shnbsd_supply_reg (char *regs, int regno) argument
64 regcache_raw_supply (current_regcache, PC_REGNUM, regs + (0 * 4));
67 regcache_raw_supply (current_regcache, SR_REGNUM, regs + (1 * 4));
70 regcache_raw_supply (current_regcache, PR_REGNUM, regs + (2 * 4));
73 regcache_raw_supply (current_regcache, MACH_REGNUM, regs + (3 * 4));
76 regcache_raw_supply (current_regcache, MACL_REGNUM, regs + (4 * 4));
83 regs + regmap[i - R0_REGNUM]);
88 shnbsd_fill_reg (char *regs, int regno) argument
93 regcache_raw_collect (current_regcache, PC_REGNUM, regs + (0 * 4));
96 regcache_raw_collect (current_regcache, SR_REGNUM, regs
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H A Duser-regs.c25 #include "user-regs.h"
61 append_user_reg (struct gdb_user_regs *regs, const char *name, argument
71 (*regs->last) = reg;
72 regs->last = &(*regs->last)->next;
95 struct gdb_user_regs *regs = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct gdb_user_regs); local
96 regs->last = &regs->first;
98 append_user_reg (regs, reg->name, reg->read,
100 return regs;
107 struct gdb_user_regs *regs = gdbarch_data (gdbarch, user_regs_data); local
146 struct gdb_user_regs *regs = gdbarch_data (gdbarch, user_regs_data); local
164 struct gdb_user_regs *regs = gdbarch_data (gdbarch, user_regs_data); local
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/haiku-fatelf/src/system/boot/platform/bios_ia32/
H A Dbios.cpp12 extern "C" void call_bios_internal(uint8 num, struct bios_regs* regs);
16 call_bios(uint8 num, struct bios_regs* regs) argument
19 call_bios_internal(num, regs);
H A Dkeyboard.cpp19 bios_regs regs; local
20 regs.eax = 0x0100;
21 call_bios(0x16, &regs);
24 if (regs.flags & ZERO_FLAG)
28 regs.eax = 0;
29 call_bios(0x16, &regs);
31 return regs.eax & 0xffff;
58 bios_regs regs; local
61 regs.eax = 0x0200;
62 call_bios(0x16, &regs);
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H A Dapm.cpp28 struct bios_regs regs; local
29 regs.eax = BIOS_APM_CHECK;
30 regs.ebx = 0;
31 call_bios(0x15, &regs);
33 if ((regs.flags & CARRY_FLAG) != 0
34 || (regs.ebx & 0xffff) != 'PM') {
40 info.version = regs.eax & 0xffff;
41 info.flags = regs.ecx & 0xffff;
54 regs.eax = BIOS_APM_DISCONNECT;
55 regs
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/haiku-fatelf/src/add-ons/kernel/drivers/graphics/radeon/
H A Dpll_access.c16 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic ) argument
24 INREG( regs, RADEON_CLOCK_CNTL_DATA);
25 INREG( regs, RADEON_CRTC_GEN_CNTL);
28 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic ) argument
50 save = INREG( regs, RADEON_CLOCK_CNTL_INDEX );
52 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp );
53 tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA );
54 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save );
59 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr ) argument
63 OUTREG8( regs, RADEON_CLOCK_CNTL_INDE
71 Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val ) argument
84 Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask ) argument
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H A Dvip.c32 vuint8 *regs = di->regs; local
36 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 );
43 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, 0,
48 INREG( regs, RADEON_VIPH_REG_DATA );
57 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,
62 *data = INREG( regs, RADEON_VIPH_REG_DATA );
72 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,
99 vuint8 *regs = di->regs; local
191 vuint8 *regs = di->regs; local
228 vuint8 *regs = di->regs; local
286 vuint8 *regs = di->regs; local
338 vuint8 *regs = di->regs; local
356 vuint8 *regs = di->regs; local
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H A DCP_setup.c130 if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) {
143 INREG( di->regs, RADEON_RBBM_STATUS ),
144 INREG( di->regs, RADEON_CP_STAT ),
145 INREG( di->regs, RADEON_AIC_TLB_ADDR ),
146 INREG( di->regs, RADEON_AIC_TLB_DATA ));
163 int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
182 OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL,
188 if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT )
204 vuint8 *regs = di->regs; local
322 vuint8 *regs = di->regs; local
373 vuint8 *regs = di->regs; local
389 vuint8 *regs = di->regs; local
429 vuint8 *regs = di->regs; local
577 vuint8 *regs = di->regs; local
637 vuint8 *regs = di->regs; local
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/haiku-fatelf/src/bin/gdb/gdb/config/alpha/
H A Dnm-osf.h46 #define ALPHA_REGSET_BASE(regsetp) ((regsetp)->regs)
/haiku-fatelf/headers/private/kernel/arch/x86/
H A Darch_hpet.h22 #define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID)
23 #define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8)
24 #define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13)
25 #define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15)
26 #define HPET_GET_VENDOR_ID(regs) (((regs)
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/haiku-fatelf/src/add-ons/accelerants/radeon/
H A Ddpms.c59 vuint8 *regs = ai->regs; local
68 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON );
70 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON );
78 old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);
82 Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );
84 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, 0, ~(RADEON_LVDS_BLON | RADEON_LVDS_ON) );
87 Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );
97 vuint8 *regs = ai->regs; local
119 vuint8 *regs = ai->regs; local
150 vuint8 *regs = ai->regs; local
172 vuint8 *regs = ai->regs; local
198 vuint8 *regs = ai->regs; local
240 vuint8 *regs = ai->regs; local
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H A Dflat_panel.c23 vuint8 *regs = ai->regs; local
25 values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH );
26 values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH );
110 vuint8 *regs = ai->regs; local
112 OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch );
113 OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch );
120 vuint8 *regs = ai->regs; local
254 vuint8 *regs = ai->regs; local
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/haiku-fatelf/src/add-ons/kernel/drivers/timer/
H A Dhpet.h23 #define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID)
24 #define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8)
25 #define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13)
26 #define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15)
27 #define HPET_GET_VENDOR_ID(regs) (((regs)
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/haiku-fatelf/src/bin/gdb/gdb/regformats/
H A Dregdef.h42 ``regs'', with ``n'' elements. */
44 void set_register_cache (struct reg *regs, int n);
/haiku-fatelf/src/system/kernel/arch/x86/32/
H A Dapm.cpp92 call_apm_bios(bios_regs *regs) argument
106 : "=a" (regs->eax), "=b" (regs->ebx), "=c" (regs->ecx), "=d" (regs->edx),
107 "=S" (regs->esi), "=m" (regs->flags)
108 : "a" (regs->eax), "b" (regs->ebx), "c" (regs
124 bios_regs regs; local
139 bios_regs regs; local
156 bios_regs regs; local
168 bios_regs regs; local
181 bios_regs regs; local
209 bios_regs regs; local
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/haiku-fatelf/src/bin/gdb/gdb/nlm/
H A Di386.c26 frame_to_registers (struct StackFrame *frame, char *regs) argument
29 mem2hex (&frame->ExceptionEAX, &regs[0 * 4 * 2], 4 * 8, 0);
32 mem2hex (&frame->ExceptionPC, &regs[8 * 4 * 2], 4 * 2, 0);
35 mem2hex (&frame->ExceptionCS, &regs[10 * 4 * 2], 4 * 3, 0);
38 mem2hex (&frame->ExceptionES, &regs[13 * 4 * 2], 4 * 1, 0);
41 mem2hex (&frame->ExceptionFS, &regs[14 * 4 * 2], 4 * 2, 0);
47 registers_to_frame (char *regs, struct StackFrame *frame) argument
50 hex2mem (&regs[0 * 4 * 2], &frame->ExceptionEAX, 4 * 8, 0);
53 hex2mem (&regs[8 * 4 * 2], &frame->ExceptionPC, 4 * 2, 0);
56 hex2mem (&regs[1
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/haiku-fatelf/src/add-ons/accelerants/matrox/engine/
H A Dmga_globals.h5 extern vuint32 *regs;
/haiku-fatelf/src/add-ons/accelerants/matrox/
H A Dglobal.h5 extern vuint32 *regs;

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