Searched refs:insn (Results 1 - 25 of 150) sorted by relevance

123456

/haiku-fatelf/src/bin/network/tcpdump/
H A Dbpf_dump.c40 struct bpf_insn *insn; local
44 insn = p->bf_insns;
47 for (i = 0; i < n; ++insn, ++i) {
48 printf("%u %u %u %u\n", insn->code,
49 insn->jt, insn->jf, insn->k);
54 for (i = 0; i < n; ++insn, ++i)
56 insn->code, insn
[all...]
/haiku-fatelf/src/bin/network/tcpdump/libpcap/
H A Dbpf_dump.c36 struct bpf_insn *insn; local
40 insn = p->bf_insns;
43 for (i = 0; i < n; ++insn, ++i) {
44 printf("%u %u %u %u\n", insn->code,
45 insn->jt, insn->jf, insn->k);
50 for (i = 0; i < n; ++insn, ++i)
52 insn->code, insn
[all...]
/haiku-fatelf/src/bin/gdb/opcodes/
H A Dm10200-dis.c27 unsigned long insn, unsigned long,
37 unsigned long insn; local
49 insn = *(unsigned char *) buffer;
52 if ((insn & 0xf0) == 0x00
53 || (insn & 0xf0) == 0x10
54 || (insn & 0xf0) == 0x20
55 || (insn & 0xf0) == 0x30
56 || ((insn & 0xf0) == 0x80
57 && (insn & 0x0c) >> 2 != (insn
[all...]
H A Davr-dis.c49 avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
50 unsigned int insn;
65 insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
67 insn = (insn & 0x01f0) >> 4; /* destination register */
69 sprintf (buf, "r%d", insn);
74 sprintf (buf, "r%d", 16 + (insn & 0xf));
76 sprintf (buf, "r%d", 16 + ((insn
258 unsigned int insn, insn2; local
[all...]
H A Dhppa-dis.c143 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
144 GET_FIELD (insn, 18, 18) << 1)
146 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
147 (GET_FIELD ((insn), 19, 19) ? 8 : 0))
376 unsigned int insn, i; local
388 insn = bfd_getb32 (buffer);
393 if ((insn & opcode->mask) == opcode->match)
409 fput_reg (GET_FIELD (insn, 1
[all...]
H A Di860-dis.c93 unsigned int insn, i; local
106 insn = bfd_getl32 (buff);
113 if ((insn & opcode->match) == opcode->match
114 && (insn & opcode->lose) == 0)
125 (*info->fprintf_func) (info->stream, ".long %#08x", insn);
134 if (((insn & 0xfc000000) == 0x48000000
135 || (insn & 0xfc000000) == 0xb0000000)
136 && (insn & 0x200))
148 grnames[(insn >> 11) & 0x1f]);
154 grnames[(insn >> 2
[all...]
H A Dor32-dis.c43 find_bytes_big (insn_ch, insn)
45 unsigned long *insn;
47 *insn =
53 printf ("find_bytes_big3: %x\n", *insn);
58 find_bytes_little (insn_ch, insn)
60 unsigned long *insn;
62 *insn =
73 or32_extract (param_ch, enc_initial, insn)
76 unsigned long insn;
128 ret += ((insn >> opc_po
262 unsigned long insn; local
[all...]
H A Darc-opc.c77 /* Various types of ARC operands, including insn suffixes. */
88 '0' SYNTAX_ST_NE enforce store insn syntax, no errors
89 '1' SYNTAX_LD_NE enforce load insn syntax, no errors
90 '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only
91 '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only
92 's' BASE base in st insn
95 'G' FLAGINSN insert F flag in "flag" insn
187 /* fake utility operand to set the 'f' flag for the "flag" insn. */
207 /* jump address; j insn (this is basically the same as 'L' except that the
212 /* jump flags; j{,l} insn valu
[all...]
H A Dm10300-dis.c27 unsigned long insn, unsigned int));
40 unsigned long insn; local
50 insn = *(unsigned char *) buffer;
53 if ((insn & 0xf3) == 0x00
54 || (insn & 0xf0) == 0x10
55 || (insn & 0xfc) == 0x3c
56 || (insn & 0xf3) == 0x41
57 || (insn & 0xf3) == 0x40
58 || (insn & 0xfc) == 0x50
59 || (insn
[all...]
H A Dtic80-dis.c140 #define M_SI(insn,op) ((((op)->flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17)))
141 #define M_LI(insn,op) ((((op)->flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15)))
142 #define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11)))
145 print_operand (info, value, insn, operand, memaddr)
148 unsigned long insn;
155 if (M_SI (insn, operand) || M_LI (insn, operan
376 unsigned long insn; local
[all...]
H A Dcgen-asm.in65 @arch@_cgen_build_insn_regex (CGEN_INSN *insn)
67 CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
68 const char *mnem = CGEN_INSN_MNEMONIC (insn);
86 /* Copy the literal mnemonic out of the insn. */
156 CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
157 reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
165 regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
166 regfree ((regex_t *) CGEN_INSN_RX (insn));
167 free (CGEN_INSN_RX (insn));
168 (CGEN_INSN_RX (insn))
[all...]
H A Dsparc-dis.c32 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
34 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
43 /* It is important that we only look at insn code bits as that is how the
185 is_delayed_branch (insn)
186 unsigned long insn;
190 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
193 if ((opcode->match & insn) == opcode->match
194 && (opcode->lose & insn)
221 unsigned long insn; local
[all...]
H A Dcgen-dis.c39 /* Return the number of decodable bits in this insn. */
41 count_decodable_bits (const CGEN_INSN *insn) argument
43 unsigned mask = CGEN_INSN_BASE_MASK (insn);
57 const CGEN_INSN *insn,
66 This ensures that any insn which is a special case of another will be
68 insn_decodable_bits = count_decodable_bits (insn);
73 int current_decodable_bits = count_decodable_bits (current_buf->insn);
79 /* Now insert the new insn. */
80 hentbuf->insn = insn;
56 add_insn_to_hash_chain(CGEN_INSN_LIST *hentbuf, const CGEN_INSN *insn, CGEN_INSN_LIST **htable, unsigned int hash) argument
116 const CGEN_INSN *insn = &insns[i]; local
[all...]
H A Dd30v-dis.c26 static int lookup_opcode PARAMS ((struct d30v_insn *insn, long num, int is_long));
28 struct d30v_insn *insn, int is_long, int show_ext));
39 struct d30v_insn insn; local
42 insn.form = (struct d30v_format *) NULL;
60 if (!(result = lookup_opcode (&insn, in1, 0)))
63 print_insn (info, memaddr, (long long) in1, &insn, 0, result);
71 if (!(result = lookup_opcode (&insn, in1, 1)))
77 print_insn (info, memaddr, num, &insn, 1, result);
82 if (!(result = lookup_opcode (&insn, in1, 0)))
85 print_insn (info, memaddr, num, &insn,
[all...]
H A Dw65-dis.c86 unsigned char insn[4]; local
97 status = info->read_memory_func (memaddr + i, insn + i, 1, info);
100 for (op = optable; op->val != insn[0]; op++)
108 int asR_W65_ABS8 = insn[1];
109 int asR_W65_ABS16 = (insn[2] << 8) + asR_W65_ABS8;
110 int asR_W65_ABS24 = (insn[3] << 16) + asR_W65_ABS16;
H A Dd10v-dis.c28 static void dis_2_short PARAMS ((unsigned long insn, bfd_vma memaddr,
30 static void dis_long PARAMS ((unsigned long insn, bfd_vma memaddr,
43 unsigned long insn; local
51 insn = bfd_getb32 (buffer);
53 status = insn & FM11;
57 dis_2_short (insn, memaddr, info, 2);
60 dis_2_short (insn, memaddr, info, 0);
63 dis_2_short (insn, memaddr, info, 1);
66 dis_long (insn, memaddr, info);
73 print_operand (oper, insn, o
226 (*info->fprintf_func) (info->stream, ".long\\t0x%08x", insn); local
299 (*info->fprintf_func) (info->stream, ".long\\t0x%08x", insn); local
[all...]
H A Dmsp430-dis.c79 unsigned short insn; local
84 insn = msp430dis_opcode (addr, info);
85 sprintf (dinfo, "0x%04x", insn);
89 (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);
98 if ((insn & opcode->bin_mask) == opcode->bin_opcode
107 if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0
108 && (0x0080 & insn) == 0)
111 msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
120 cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
124 msp430_doubleoperand (info, opcode, addr, insn, op
[all...]
H A Dtic30-dis.c31 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
88 struct instruction insn = { 0, NULL, NULL }; local
96 if (!get_tic30_instruction (insn_word, &insn))
102 if (!print_two_operand (info, insn_word, &insn))
106 if (!print_three_operand (info, insn_word, &insn))
111 if (!print_par_insn (info, insn_word, &insn))
115 if (!print_branch (info, insn_word, &insn))
[all...]
H A Di370-dis.c36 i370_insn_t insn; local
47 /* Cast the bytes into the insn (in a host-endian indep way) */
48 insn.i[0] = (buffer[0] << 24) & 0xff000000;
49 insn.i[0] |= (buffer[1] << 16) & 0xff0000;
50 insn.i[0] |= (buffer[2] << 8) & 0xff00;
51 insn.i[0] |= buffer[3] & 0xff;
52 insn.i[1] = (buffer[4] << 24) & 0xff000000;
53 insn.i[1] |= (buffer[5] << 16) & 0xff0000;
66 masked = insn;
84 insn
[all...]
H A Dcris-dis.c145 get_opcode_entry (insn, prefix_insn)
146 unsigned int insn;
150 insn code. Each entry is initialized when found to be NULL. */
243 && prefix_opc_table[insn] != NULL)
244 max_matchedp = prefix_opc_table[insn];
245 else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
246 max_matchedp = opc_table[insn];
264 if ((opcodep->match & insn) == opcodep->match
265 && (opcodep->lose & insn) == 0
268 insn,
1198 unsigned int insn; local
[all...]
/haiku-fatelf/src/bin/gdb/bfd/
H A Dxtensa-modules.c201 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
204 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
209 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
213 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
217 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
220 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
225 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
229 insn[0] = (insn[
198 Field_t_Slot_inst_get(const xtensa_insnbuf insn) argument
206 Field_t_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
214 Field_s_Slot_inst_get(const xtensa_insnbuf insn) argument
222 Field_s_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
230 Field_r_Slot_inst_get(const xtensa_insnbuf insn) argument
238 Field_r_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
246 Field_op2_Slot_inst_get(const xtensa_insnbuf insn) argument
254 Field_op2_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
262 Field_op1_Slot_inst_get(const xtensa_insnbuf insn) argument
270 Field_op1_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
278 Field_op0_Slot_inst_get(const xtensa_insnbuf insn) argument
286 Field_op0_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
294 Field_n_Slot_inst_get(const xtensa_insnbuf insn) argument
302 Field_n_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
310 Field_m_Slot_inst_get(const xtensa_insnbuf insn) argument
318 Field_m_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
326 Field_sr_Slot_inst_get(const xtensa_insnbuf insn) argument
335 Field_sr_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
345 Field_thi3_Slot_inst_get(const xtensa_insnbuf insn) argument
353 Field_thi3_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
361 Field_op0_Slot_inst16a_get(const xtensa_insnbuf insn) argument
369 Field_op0_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
377 Field_t_Slot_inst16b_get(const xtensa_insnbuf insn) argument
385 Field_t_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
393 Field_r_Slot_inst16b_get(const xtensa_insnbuf insn) argument
401 Field_r_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
409 Field_op0_Slot_inst16b_get(const xtensa_insnbuf insn) argument
417 Field_op0_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
425 Field_z_Slot_inst16b_get(const xtensa_insnbuf insn) argument
433 Field_z_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
441 Field_i_Slot_inst16b_get(const xtensa_insnbuf insn) argument
449 Field_i_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
457 Field_s_Slot_inst16b_get(const xtensa_insnbuf insn) argument
465 Field_s_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
473 Field_t_Slot_inst16a_get(const xtensa_insnbuf insn) argument
481 Field_t_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
489 Field_bbi4_Slot_inst_get(const xtensa_insnbuf insn) argument
497 Field_bbi4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
505 Field_bbi_Slot_inst_get(const xtensa_insnbuf insn) argument
514 Field_bbi_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
524 Field_imm12_Slot_inst_get(const xtensa_insnbuf insn) argument
532 Field_imm12_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
540 Field_imm8_Slot_inst_get(const xtensa_insnbuf insn) argument
548 Field_imm8_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
556 Field_s_Slot_inst16a_get(const xtensa_insnbuf insn) argument
564 Field_s_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
572 Field_imm12b_Slot_inst_get(const xtensa_insnbuf insn) argument
581 Field_imm12b_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
591 Field_imm16_Slot_inst_get(const xtensa_insnbuf insn) argument
599 Field_imm16_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
607 Field_offset_Slot_inst_get(const xtensa_insnbuf insn) argument
615 Field_offset_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
623 Field_r_Slot_inst16a_get(const xtensa_insnbuf insn) argument
631 Field_r_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
639 Field_sa4_Slot_inst_get(const xtensa_insnbuf insn) argument
647 Field_sa4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
655 Field_sae4_Slot_inst_get(const xtensa_insnbuf insn) argument
663 Field_sae4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
671 Field_sae_Slot_inst_get(const xtensa_insnbuf insn) argument
680 Field_sae_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
690 Field_sal_Slot_inst_get(const xtensa_insnbuf insn) argument
699 Field_sal_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
709 Field_sargt_Slot_inst_get(const xtensa_insnbuf insn) argument
718 Field_sargt_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
728 Field_sas4_Slot_inst_get(const xtensa_insnbuf insn) argument
736 Field_sas4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
744 Field_sas_Slot_inst_get(const xtensa_insnbuf insn) argument
753 Field_sas_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
763 Field_sr_Slot_inst16a_get(const xtensa_insnbuf insn) argument
772 Field_sr_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
782 Field_sr_Slot_inst16b_get(const xtensa_insnbuf insn) argument
791 Field_sr_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
801 Field_st_Slot_inst_get(const xtensa_insnbuf insn) argument
810 Field_st_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
820 Field_st_Slot_inst16a_get(const xtensa_insnbuf insn) argument
829 Field_st_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
839 Field_st_Slot_inst16b_get(const xtensa_insnbuf insn) argument
848 Field_st_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
858 Field_imm4_Slot_inst_get(const xtensa_insnbuf insn) argument
866 Field_imm4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
874 Field_imm4_Slot_inst16a_get(const xtensa_insnbuf insn) argument
882 Field_imm4_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
890 Field_imm4_Slot_inst16b_get(const xtensa_insnbuf insn) argument
898 Field_imm4_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
906 Field_mn_Slot_inst_get(const xtensa_insnbuf insn) argument
915 Field_mn_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument
925 Field_i_Slot_inst16a_get(const xtensa_insnbuf insn) argument
933 Field_i_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
941 Field_imm6lo_Slot_inst16a_get(const xtensa_insnbuf insn) argument
949 Field_imm6lo_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
957 Field_imm6lo_Slot_inst16b_get(const xtensa_insnbuf insn) argument
965 Field_imm6lo_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
973 Field_imm6hi_Slot_inst16a_get(const xtensa_insnbuf insn) argument
981 Field_imm6hi_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
989 Field_imm6hi_Slot_inst16b_get(const xtensa_insnbuf insn) argument
997 Field_imm6hi_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
1005 Field_imm7lo_Slot_inst16a_get(const xtensa_insnbuf insn) argument
1013 Field_imm7lo_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
1021 Field_imm7lo_Slot_inst16b_get(const xtensa_insnbuf insn) argument
1029 Field_imm7lo_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
1037 Field_imm7hi_Slot_inst16a_get(const xtensa_insnbuf insn) argument
1045 Field_imm7hi_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
1053 Field_imm7hi_Slot_inst16b_get(const xtensa_insnbuf insn) argument
1061 Field_imm7hi_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
1069 Field_z_Slot_inst16a_get(const xtensa_insnbuf insn) argument
1077 Field_z_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
1085 Field_imm6_Slot_inst16a_get(const xtensa_insnbuf insn) argument
1094 Field_imm6_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
1104 Field_imm6_Slot_inst16b_get(const xtensa_insnbuf insn) argument
1113 Field_imm6_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
1123 Field_imm7_Slot_inst16a_get(const xtensa_insnbuf insn) argument
1132 Field_imm7_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument
1142 Field_imm7_Slot_inst16b_get(const xtensa_insnbuf insn) argument
1151 Field_imm7_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument
7909 Slot_inst_decode(const xtensa_insnbuf insn) argument
8628 Slot_inst16b_decode(const xtensa_insnbuf insn) argument
8677 Slot_inst16a_decode(const xtensa_insnbuf insn) argument
8697 Slot_x24_Format_inst_0_get(const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) argument
8704 Slot_x24_Format_inst_0_set(xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) argument
8711 Slot_x16a_Format_inst16a_0_get(const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) argument
8718 Slot_x16a_Format_inst16a_0_set(xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) argument
8725 Slot_x16b_Format_inst16b_0_get(const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) argument
8732 Slot_x16b_Format_inst16b_0_set(xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) argument
9015 Format_x24_encode(xtensa_insnbuf insn) argument
9021 Format_x16a_encode(xtensa_insnbuf insn) argument
9027 Format_x16b_encode(xtensa_insnbuf insn) argument
9046 format_decoder(const xtensa_insnbuf insn) argument
9077 length_decoder(const char *insn) argument
[all...]
H A Delf32-or32.c293 unsigned long insn; local
298 insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
299 insn += symbol->section->output_section->vma;
300 insn += symbol->section->output_offset;
301 insn += symbol->value;
302 bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
323 unsigned short insn; local
328 insn = bfd_get_16 (abfd, (bfd_byte *) data + addr);
329 insn += symbol->section->output_section->vma;
330 insn
353 unsigned char insn; local
460 unsigned long insn; local
487 unsigned long insn, tmp; local
521 unsigned long insn, tmp; local
[all...]
/haiku-fatelf/src/bin/gdb/gdb/gdbserver/
H A Dlinux-arm-low.c76 unsigned long insn; local
78 (*the_target->read_memory) (where, (char *) &insn, 4);
79 if (insn == arm_breakpoint)
H A Dlinux-sh-low.c82 unsigned short insn; local
84 (*the_target->read_memory) (where, (char *) &insn, 2);
85 if (insn == sh_breakpoint)
/haiku-fatelf/src/bin/gdb/gdb/
H A Dtramp-frame.c94 for (ti = 0; tramp->insn[ti].bytes != TRAMP_SENTINEL_INSN; ti++)
100 bfd_byte buf[sizeof (tramp->insn[0])];
101 ULONGEST insn; local
102 if (tramp->insn[i].bytes == TRAMP_SENTINEL_INSN)
108 insn = extract_unsigned_integer (buf, tramp->insn_size);
109 if (tramp->insn[i].bytes != (insn & tramp->insn[i].mask))
157 for (i = 0; i < ARRAY_SIZE (tramp_frame->insn); i++)
159 if (tramp_frame->insn[
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