Searched refs:src0 (Results 1 - 22 of 22) sorted by relevance

/haiku-buildtools/gcc/gcc/testsuite/gcc.dg/vect/
H A Dpr43432.c5 void vector_fmul_reverse_c(float *dst, const float *src0, const float *src1, argument
10 dst[i] = src0[i] * src1[-i];
/haiku-buildtools/gcc/gcc/testsuite/gcc.c-torture/compile/
H A D20070520-1.c8 const uint8_t * const src0 = src+3-stride; local
11 int H = src0[1] - src0[-1];
15 H += k*(src0[k] - src0[-k]);
/haiku-buildtools/legacy/binutils/gas/config/
H A Dbfin-aux.h29 int op0, REG_T dst, REG_T src0, REG_T src1, int w0);
34 int op0, REG_T dst, REG_T src0, REG_T src1, int w0);
38 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1);
41 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, REG_T src1,
93 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc);
H A Dtc-bfin.c1235 REG_T dst, REG_T src0, REG_T src1, int w0)
1259 ASSIGN_R (src0);
1268 REG_T dst, REG_T src0, REG_T src1, int w0)
1290 ASSIGN_R (src0);
1298 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
1309 ASSIGN_R (src0);
1316 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, argument
1326 ASSIGN_R (src0);
1718 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc) argument
1722 ASSIGN_R (src0);
1233 bfin_gen_dsp32mac(int op1, int MM, int mmod, int w1, int P, int h01, int h11, int h00, int h10, int op0, REG_T dst, REG_T src0, REG_T src1, int w0) argument
1266 bfin_gen_dsp32mult(int op1, int MM, int mmod, int w1, int P, int h01, int h11, int h00, int h10, int op0, REG_T dst, REG_T src0, REG_T src1, int w0) argument
1297 bfin_gen_dsp32alu(int HL, int aopcde, int aop, int s, int x, REG_T dst0, REG_T dst1, REG_T src0, REG_T src1) argument
[all...]
H A Dbfin-parse.y32 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
33 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
35 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
37 dst, src0, src1, w0)
39 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
41 dst, src0, src1, w0)
43 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
44 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
112 #define COMP3OP(dst, src0, src1, opc) \
113 bfin_gen_comp3op (src0, src
[all...]
/haiku-buildtools/legacy/binutils/opcodes/
H A Dbfin-dis.c471 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf) argument
476 s0 = dregs_hi (src0);
478 s0 = dregs_lo (src0);
492 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf) argument
520 decode_multfunc (h0, h1, src0, src1, outf);
1430 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1434 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); local
1437 if (opc == 5 && src1 == src0)
1441 OUTS (outf, pregs (src0));
1448 OUTS (outf, dregs (src0));
2568 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
2649 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
2700 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); local
3599 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...]
/haiku-buildtools/binutils/opcodes/
H A Dbfin-dis.c557 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf) argument
562 s0 = dregs_hi (src0);
564 s0 = dregs_lo (src0);
578 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf) argument
604 decode_multfunc (h0, h1, src0, src1, outf);
1647 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1651 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); local
1654 if (opc == 5 && src1 == src0)
1658 OUTS (outf, pregs (src0));
1665 OUTS (outf, dregs (src0));
2946 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3030 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); local
3081 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); local
3887 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...]
/haiku-buildtools/gcc/gcc/testsuite/gcc.target/i386/
H A Dsha256rnds2-2.c35 compute_sha256rnds2 (int *src0, int *src1, int *src2, int *res) argument
37 int wk[2] = { src0[0], src0[1] };
/haiku-buildtools/gcc/gcc/
H A Dasan.c542 asan_mem_ref *src0,
834 src0->start = source0;
835 src0->access_size = access_size;
890 asan_mem_ref src0, src1, dest; local
891 asan_mem_ref_init (&src0, NULL, 1);
899 &src0, &src0_len, &src0_is_store,
904 if (src0.start != NULL_TREE
905 && !has_mem_ref_been_instrumented (&src0, src0_len))
1924 asan_mem_ref src0, src1, dest; local
1925 asan_mem_ref_init (&src0, NUL
541 get_mem_refs_of_builtin_call(const gcall *call, asan_mem_ref *src0, tree *src0_len, bool *src0_is_store, asan_mem_ref *src1, tree *src1_len, bool *src1_is_store, asan_mem_ref *dst, tree *dst_len, bool *dst_is_store, bool *dest_is_deref, bool *intercepted_p) argument
[all...]
H A Drtlanal.c1364 rtx src0 = XEXP (src, 0);
1366 HOST_WIDE_INT offset = GET_MODE_UNIT_SIZE (GET_MODE (src0)) * c0;
1372 simplify_subreg_regno (REGNO (src0), GET_MODE (src0),
1351 rtx src0 = XEXP (src, 0); local
/haiku-buildtools/binutils/gas/config/
H A Dtc-bfin.c1174 REG_T dst, REG_T src0, REG_T src1, int w0)
1198 ASSIGN_R (src0);
1207 REG_T dst, REG_T src0, REG_T src1, int w0)
1229 ASSIGN_R (src0);
1237 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
1248 ASSIGN_R (src0);
1255 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,
1265 ASSIGN_R (src0);
1656 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
1660 ASSIGN_R (src0);
1171 bfin_gen_dsp32mac(int op1, int MM, int mmod, int w1, int P, int h01, int h11, int h00, int h10, int op0, REG_T dst, REG_T src0, REG_T src1, int w0) argument
1204 bfin_gen_dsp32mult(int op1, int MM, int mmod, int w1, int P, int h01, int h11, int h00, int h10, int op0, REG_T dst, REG_T src0, REG_T src1, int w0) argument
1235 bfin_gen_dsp32alu(int HL, int aopcde, int aop, int s, int x, REG_T dst0, REG_T dst1, REG_T src0, REG_T src1) argument
1254 bfin_gen_dsp32shift(int sopcde, REG_T dst0, REG_T src0, REG_T src1, int sop, int HLs) argument
1655 bfin_gen_comp3op(REG_T src0, REG_T src1, REG_T dst, int opc) argument
2487 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); local
[all...]
H A Dbfin-parse.y28 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
29 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
31 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
33 dst, src0, src1, w0)
35 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
37 dst, src0, src1, w0)
39 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
40 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
108 #define COMP3OP(dst, src0, src1, opc) \
109 bfin_gen_comp3op (src0, src
[all...]
/haiku-buildtools/gcc/gcc/config/fr30/
H A Dfr30.c996 rtx src0;
1001 src0 = operand_subword (src, 0, TRUE, mode);
1004 emit_move_insn (adjust_address (dest, SImode, 0), src0);
994 rtx src0; local
/haiku-buildtools/legacy/binutils/gas/
H A Dbfin-parse.c423 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
424 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
426 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
428 dst, src0, src1, w0)
430 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
432 dst, src0, src1, w0)
434 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
435 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
503 #define COMP3OP(dst, src0, src1, opc) \
504 bfin_gen_comp3op (src0, src
[all...]
/haiku-buildtools/gcc/gcc/config/lm32/
H A Dlm32.c94 static rtx emit_add (rtx dest, rtx src0, rtx src1);
173 emit_add (rtx dest, rtx src0, rtx src1) argument
176 insn = emit_insn (gen_addsi3 (dest, src0, src1));
/haiku-buildtools/gcc/gcc/config/m32c/
H A Dm32c.c3931 rtx op0, src0, p; local
3958 src0 = op0;
3961 src0 = gen_reg_rtx (GET_MODE (op0));
3962 emit_move_insn (src0, op0);
4003 case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
4004 case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
4005 case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
4006 case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
4007 case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
4008 case 5: p = gen_iorqi3_24 (op0, src0, GEN_IN
[all...]
/haiku-buildtools/binutils/gas/
H A Dbfin-parse.c74 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
75 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
77 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
79 dst, src0, src1, w0)
81 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
83 dst, src0, src1, w0)
85 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
86 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
154 #define COMP3OP(dst, src0, src1, opc) \
155 bfin_gen_comp3op (src0, src
[all...]
/haiku-buildtools/gcc/gcc/config/stormy16/
H A Dstormy16.c1048 emit_addhi3_postreload (rtx dest, rtx src0, rtx src1)
1052 set = gen_rtx_SET (VOIDmode, dest, gen_rtx_PLUS (HImode, src0, src1));
1996 rtx dest, rtx src0, rtx src1)
2003 emit_move_insn (src0, const0_rtx);
2010 w_src0 = simplify_gen_subreg (word_mode, src0, mode,
1046 emit_addhi3_postreload(rtx dest, rtx src0, rtx src1) argument
1988 xstormy16_expand_arith(machine_mode mode, enum rtx_code code, rtx dest, rtx src0, rtx src1) argument
/haiku-buildtools/gcc/gcc/config/tilepro/
H A Dtilepro.c2619 src0 and src1 (if DO_SRC1 is true) is converted to SRC_MODE. */
2625 rtx src0, rtx src1, bool do_src1)
2629 if (src0 == const0_rtx)
2630 src0 = CONST0_RTX (src_mode);
2632 src0 = gen_lowpart (src_mode, src0);
2642 emit_insn ((*gen) (dest, src0, src1));
2615 tilepro_expand_builtin_vector_binop(rtx (gen) rtx, rtx, rtx), machine_mode dest_mode, rtx dest, machine_mode src_mode, rtx src0, rtx src1, bool do_src1) argument
/haiku-buildtools/gcc/gcc/config/tilegx/
H A Dtilegx.c2825 src0 and src1 (if DO_SRC1 is true) is converted to SRC_MODE. */
2831 rtx src0, rtx src1, bool do_src1)
2835 if (src0 == const0_rtx)
2836 src0 = CONST0_RTX (src_mode);
2838 src0 = gen_lowpart (src_mode, src0);
2848 emit_insn ((*gen) (dest, src0, src1));
2821 tilegx_expand_builtin_vector_binop(rtx (gen) rtx, rtx, rtx), machine_mode dest_mode, rtx dest, machine_mode src_mode, rtx src0, rtx src1, bool do_src1) argument
/haiku-buildtools/legacy/gcc/gcc/
H A Dreload1.c10351 rtx src0 = XEXP (src, 0);
10352 if (GET_CODE (src0) == REG)
10354 if (REGNO (src0) != regno
10357 reg_base_reg[regno] = REGNO (src0);
10317 rtx src0 = XEXP (src, 0); local
/haiku-buildtools/gcc/gcc/config/arc/
H A Darc.c8220 rtx src0 = XEXP (src, 0);
8224 if (rtx_equal_p (src1, dst) && !rtx_equal_p (src0, dst)
8227 && REG_P (src0))
8230 src1, src0));
8218 rtx src0 = XEXP (src, 0); local

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