Searched refs:latency (Results 1 - 25 of 30) sorted by relevance

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/haiku-buildtools/gcc/gcc/
H A Dddg.h88 int latency; member in struct:ddg_edge
H A Dexpmed.h42 The "latency" field holds the minimum possible latency of the
46 any leaf to the root. Hence latency(a op b) is defined as zero for
47 leaves and rtx_cost(op) + max(latency(a), latency(b)) otherwise. */
51 short latency; /* The latency of the multiplication sequence. */ member in struct:mult_cost
58 || ((X)->cost == (Y) && (X)->latency < (Y)))
63 lower "cost". If "cost"s are tied, the lower latency is cheaper. */
66 && (X)->latency < (
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H A Dddg.c208 /* Computes the dependence parameters (latency, distance etc.), creates
215 int latency, distance = 0;
266 latency = dep_cost (link);
267 e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
734 dep_c, e->latency, e->distance, INSN_UID (e->dest->insn));
789 fprintf (file, "label: \"%d_%d\"}\n", e->latency, e->distance);
830 e->latency = l;
881 length += backarc->latency;
1211 at-least as large as the count of U_NODE plus the latency between them.
1227 && (v_node->aux.count < u_node->aux.count + e->latency))
214 int latency, distance = 0; local
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H A Dexpmed.c2438 alg_out->cost.latency = cost_limit->latency + 1;
2441 || (cost_limit->cost == 0 && cost_limit->latency <= 0))
2459 alg_out->cost.latency = 0;
2474 alg_out->cost.latency = zero_cost (speed);
2568 new_limit.latency = best_cost.latency - op_cost;
2572 alg_in->cost.latency += op_cost;
2598 new_limit.latency = best_cost.latency
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H A Dmodulo-sched.c1821 'l(u)' is the latency of u.
1954 int earliest = p_st + e->latency - (e->distance * ii);
1983 int latest = s_st - e->latency + (e->distance * ii);
2062 whose dependence latency is zero.
2098 && ((SCHED_TIME (e->src) + e->latency - (e->distance * ii)) ==
2100 && e->latency == 0
2101 we use the fact that latency is non-negative:
2103 SCHED_TIME (e->src) + e->latency - (e->distance * ii)) <=
2123 && ((SCHED_TIME (e->dest) - e->latency + (e->distance * ii)) ==
2125 && e->latency
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H A Dgenautomata.c388 int latency;
1331 DECL_BYPASS (decl)->latency = XINT (def, 0);
2509 bypass->latency = DECL_BYPASS (model)->latency;
2572 automata) and correctness of their attributes (insn latency times
2580 error ("define_insn_reservation `%s' has negative latency time",
2591 if (DECL_BYPASS (decl)->latency < 0)
2592 error ("define_bypass `%s - %s' has negative latency time",
7886 int i, max, latency;
7895 latency
384 int latency; member in struct:bypass_decl
7858 int i, max, latency; local
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/haiku-buildtools/gcc/gmp/mpn/x86/pentium4/sse2/
H A Ddive_1.asm34 C will be about 9+2*4+2*2+10*4+19+12 = 92 cycles latency, though some of
142 C latency
H A Dmode1o.asm116 C latency
/haiku-buildtools/gcc/gmp/mpn/power/
H A Dlshift.asm43 stu 7,-4(9) C store previous result during read latency
H A Drshift.asm41 stu 7,4(9) C store previous result during read latency
/haiku-buildtools/gcc/gmp/mpn/alpha/
H A Dmode1o.asm42 C In each case, the load latency, loop control, and extra carry bit handling
57 C there would cost cycles, but we can hide them under the mulq latency.
/haiku-buildtools/gcc/gmp/mpn/ia64/
H A Dgcd_1.asm64 C The loop is not as fast as one might hope, since there's extra latency
95 C up with a 10 cycle replay for not forcibly scheduling the shr.u latency.
H A Dlorrshift.asm28 C have a latency of 4 (on Itanium) or 3 (on Itanium 2). Poor scheduling of
/haiku-buildtools/gcc/gmp/mpn/x86/k6/
H A Ddivrem_1.asm47 C The low-latency K6 multiply might be thought to suit a mul-by-inverse, but
H A Dmode1o.asm117 C hiding the loop control under the imul latency.
/haiku-buildtools/gcc/gmp/mpn/x86/k7/
H A Dmode1o.asm129 C Out of order execution hides the load latency for the source data, so no
H A Dsqr_basecase.asm85 C mul latency and the second gets store to load forwarding.
/haiku-buildtools/gcc/gmp/mpn/x86/p6/
H A Dmode1o.asm119 C of order execution hides the load latency.
H A Ddive_1.asm133 C of order execution hides the load latency.
/haiku-buildtools/gcc/gmp/mpn/x86_64/
H A Dmode1o.asm50 C hide the latency otherwise.
/haiku-buildtools/gcc/libgcc/config/arc/ieee-754/arc600-mul64/
H A Ddivsf3.S250 ; load latency
/haiku-buildtools/gcc/libgcc/config/arc/ieee-754/
H A Ddivsf3-stdmul.S146 ; load latency
/haiku-buildtools/gcc/gmp/mpn/m88k/
H A Dmul_1.s34 ; pipeline stalls 2 cycles due to WB contention and 1 cycle due to latency.)
/haiku-buildtools/gcc/gmp/mpn/x86/k6/mmx/
H A Ddive_1.asm200 C latency. Having imul at the top of the loop gives 11.5 c/l instead of 12,
/haiku-buildtools/gcc/libgcc/config/msp430/
H A Dlib2hw_mul.S31 NOP ; Account for latency

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