/haiku-buildtools/gcc/gcc/ |
H A D | ddg.h | 88 int latency; member in struct:ddg_edge
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H A D | expmed.h | 42 The "latency" field holds the minimum possible latency of the 46 any leaf to the root. Hence latency(a op b) is defined as zero for 47 leaves and rtx_cost(op) + max(latency(a), latency(b)) otherwise. */ 51 short latency; /* The latency of the multiplication sequence. */ member in struct:mult_cost 58 || ((X)->cost == (Y) && (X)->latency < (Y))) 63 lower "cost". If "cost"s are tied, the lower latency is cheaper. */ 66 && (X)->latency < ( [all...] |
H A D | ddg.c | 208 /* Computes the dependence parameters (latency, distance etc.), creates 215 int latency, distance = 0; 266 latency = dep_cost (link); 267 e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance); 734 dep_c, e->latency, e->distance, INSN_UID (e->dest->insn)); 789 fprintf (file, "label: \"%d_%d\"}\n", e->latency, e->distance); 830 e->latency = l; 881 length += backarc->latency; 1211 at-least as large as the count of U_NODE plus the latency between them. 1227 && (v_node->aux.count < u_node->aux.count + e->latency)) 214 int latency, distance = 0; local [all...] |
H A D | expmed.c | 2438 alg_out->cost.latency = cost_limit->latency + 1; 2441 || (cost_limit->cost == 0 && cost_limit->latency <= 0)) 2459 alg_out->cost.latency = 0; 2474 alg_out->cost.latency = zero_cost (speed); 2568 new_limit.latency = best_cost.latency - op_cost; 2572 alg_in->cost.latency += op_cost; 2598 new_limit.latency = best_cost.latency [all...] |
H A D | modulo-sched.c | 1821 'l(u)' is the latency of u. 1954 int earliest = p_st + e->latency - (e->distance * ii); 1983 int latest = s_st - e->latency + (e->distance * ii); 2062 whose dependence latency is zero. 2098 && ((SCHED_TIME (e->src) + e->latency - (e->distance * ii)) == 2100 && e->latency == 0 2101 we use the fact that latency is non-negative: 2103 SCHED_TIME (e->src) + e->latency - (e->distance * ii)) <= 2123 && ((SCHED_TIME (e->dest) - e->latency + (e->distance * ii)) == 2125 && e->latency [all...] |
H A D | genautomata.c | 388 int latency; 1331 DECL_BYPASS (decl)->latency = XINT (def, 0); 2509 bypass->latency = DECL_BYPASS (model)->latency; 2572 automata) and correctness of their attributes (insn latency times 2580 error ("define_insn_reservation `%s' has negative latency time", 2591 if (DECL_BYPASS (decl)->latency < 0) 2592 error ("define_bypass `%s - %s' has negative latency time", 7886 int i, max, latency; 7895 latency 384 int latency; member in struct:bypass_decl 7858 int i, max, latency; local [all...] |
/haiku-buildtools/gcc/gmp/mpn/x86/pentium4/sse2/ |
H A D | dive_1.asm | 34 C will be about 9+2*4+2*2+10*4+19+12 = 92 cycles latency, though some of 142 C latency
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H A D | mode1o.asm | 116 C latency
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/haiku-buildtools/gcc/gmp/mpn/power/ |
H A D | lshift.asm | 43 stu 7,-4(9) C store previous result during read latency
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H A D | rshift.asm | 41 stu 7,4(9) C store previous result during read latency
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/haiku-buildtools/gcc/gmp/mpn/alpha/ |
H A D | mode1o.asm | 42 C In each case, the load latency, loop control, and extra carry bit handling 57 C there would cost cycles, but we can hide them under the mulq latency.
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/haiku-buildtools/gcc/gmp/mpn/ia64/ |
H A D | gcd_1.asm | 64 C The loop is not as fast as one might hope, since there's extra latency 95 C up with a 10 cycle replay for not forcibly scheduling the shr.u latency.
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H A D | lorrshift.asm | 28 C have a latency of 4 (on Itanium) or 3 (on Itanium 2). Poor scheduling of
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/haiku-buildtools/gcc/gmp/mpn/x86/k6/ |
H A D | divrem_1.asm | 47 C The low-latency K6 multiply might be thought to suit a mul-by-inverse, but
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H A D | mode1o.asm | 117 C hiding the loop control under the imul latency.
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/haiku-buildtools/gcc/gmp/mpn/x86/k7/ |
H A D | mode1o.asm | 129 C Out of order execution hides the load latency for the source data, so no
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H A D | sqr_basecase.asm | 85 C mul latency and the second gets store to load forwarding.
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/haiku-buildtools/gcc/gmp/mpn/x86/p6/ |
H A D | mode1o.asm | 119 C of order execution hides the load latency.
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H A D | dive_1.asm | 133 C of order execution hides the load latency.
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/haiku-buildtools/gcc/gmp/mpn/x86_64/ |
H A D | mode1o.asm | 50 C hide the latency otherwise.
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/haiku-buildtools/gcc/libgcc/config/arc/ieee-754/arc600-mul64/ |
H A D | divsf3.S | 250 ; load latency
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/haiku-buildtools/gcc/libgcc/config/arc/ieee-754/ |
H A D | divsf3-stdmul.S | 146 ; load latency
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/haiku-buildtools/gcc/gmp/mpn/m88k/ |
H A D | mul_1.s | 34 ; pipeline stalls 2 cycles due to WB contention and 1 cycle due to latency.)
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/haiku-buildtools/gcc/gmp/mpn/x86/k6/mmx/ |
H A D | dive_1.asm | 200 C latency. Having imul at the top of the loop gives 11.5 c/l instead of 12,
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/haiku-buildtools/gcc/libgcc/config/msp430/ |
H A D | lib2hw_mul.S | 31 NOP ; Account for latency
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