Searched refs:Rt (Results 1 - 3 of 3) sorted by relevance
| /haiku-buildtools/binutils/opcodes/ |
| H A D | aarch64-tbl.h | 2760 CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF),
2761 CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF),
2986 CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0),
2987 CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0),
2988 CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE),
2991 CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0),
2992 CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0),
2993 CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE),
2994 CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
2995 CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM
[all...] |
| /haiku-buildtools/binutils/gas/testsuite/gas/arm/ |
| H A D | sp-pc-validations-bad-t.s | 53 @ LDRB<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRBT
136 @ LDRH<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRHT
|
| /haiku-buildtools/binutils/gas/config/ |
| H A D | tc-arm.c | 7190 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
9119 unsigned Rt = inst.operands[0].reg;
9121 if (thumb_mode && Rt == REG_SP)
9133 if (!inst.operands[0].isvec && Rt == REG_PC)
9142 inst.instruction |= (Rt << 12);
9148 unsigned Rt = inst.operands[1].reg;
9151 reject_bad_reg (Rt);
9152 else if (Rt == REG_PC)
9166 inst.instruction |= (Rt << 12);
9118 unsigned Rt = inst.operands[0].reg; local
9147 unsigned Rt = inst.operands[1].reg; local
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